FREE LOGIC DESIGN ASIC FPGA RESUME SAMPLES

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Resume 1

Samples represent that of an actual working technical professional found on the WEB and modified to protect the privacy of these professionals. Human names, company names, colleges, software product names are intentionally made up.

Scott Williams

OBJECTIVE:

Seeking a challenging and rewarding contracts in ASIC/FPGA Design & Verification

EXPERIENCE SUMMARY:

Overall experience of over 10 years in ASIC/FPGA Design/Verification
Verified Fibre Channel – 1 and Fibre Channel Arbitration Loop RTL
Developed TCP/IP Functional Models in SystemC and verified the TCP RTL implementation
Designed and Verified ZBT SRAM and Flash interface for LEXRA RISC Processor
Designed and Verified a Ingress FPGA [Virtex II] for Nortel s Gigabit Ethernet line card
Verified SPI-4 Soft core and Synthesised the same towards Virtex II FPGA
Designed and Verified USB1.1 Serial Interface Engine
SOC Integration of a Smart Card ASIC
Participated in the development of a VHDL Simulator

SKILL SET:

Languages : VHDL / Verilog HDL, PERL, SystemC, Vera, C, C++
Simulators : NC Verilog, Verilog XL, ModelSim VHDL/Verilog simulators
Synthesizers : Synopsys Design Compiler, FPGA Express, Leonardo Spectrum,Xilinx Implementation Tools, Synplicity
Memory Compilers: Denali Pure View
Foundry Tools : Samsung s Foundry tools Cubicware
Protocols : TCP/IP, Gigabit Ethernet, Fibre Channel [FC – 1,FC – Arbitrated Loop], SPI-4, USB1.1, EP1284 and ISA

EDUCATION:

M.S. Electrical and Electronics Engineering

PROFESSTIONAL EXPERIENCE:

Created a detailed test-plan to verify the Fibre Channel [FC – 1 and FC – Arbitration Loop] RTL and verified the RTL as per the test plan
Designed a Word Builder for the FC -1 block, integrated in the FC-1 RTL and verified the same.
Verified the RTL implementation of TCP/IP Stack. A detailed test plan was created and SystemC models of the functional blocks were written to test the whole of TCP/IP Implementation.
Designed and verified the LEXRA RISC Processor Interface with the functional blocks and verified the same.
Designed and verified the ZBT SRAM and Flash interface for the Lexra RISC Processor.
Integrated all functional RTL modules and created a system level top. Perl scripts where written to manage the files and test cases.
Created the Vera testbench environment for the whole chip.

SPI-4 Core:

Modified the SPI-4 soft core both on the Sink and Source data paths.
Synthesized the modified RTL code on Synplifypro and implement the netlist on Xilinx Implementation tools targeting to Xilinx virtex II series.
Verified the RTL and post layout netlist for functionality and timing.

Ingress FPGA for line card:

Designed and implemented the Network Processor interface on the Ingress traffic flow towards the Switch fabric. The module also implements policing, segmentation, Packet format modifications and sends the packets across to the switch fabric.
Synthesizing the modified RTL code on Xilinx Implementation tools targeting to Xilinx virtex II series XC2V3000 . Gate count of the complete Ingress FPGA 1,800,000 gates.
Modified the Accelar Simulation Environment Nortel functional simulation environment used for Verification used the same to verify the modified RTL code and synthesized gate level netlist. The job involved understanding the Accelar simulation environment and modifying the same in accordance with the new requirement.
Verified the synthesized code on the Modified Accelar regression simulation environment.

Trojan ASIC – USB Smart Card Solution:

Synthesized the DesignWare 8051 of Synopsys Inc towards Samsung 0.35u STD90 technology on Synopsys Design Compiler.
Designed testbench to test the DesignWare 8051 functionality.
Mapped to whole design to XILINX FPGA – virtex series – using the Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. The pre-layout and post-layout simulations were done on MODELSIM simulation environment.
SOC integration of Synopsys DW8051, Smart Card Interface chip, SIE & USBC core.
Project managed the whole simulation work of the USB-Smart Card.
Enhanced already present Smart Card Device Model.
Responsible for testing & debugging of the functionality of the design.

USB SIE Serial Interface Engine :

Designed & tested of all the modules of Serial Interface Engine.
Project managed the whole simulation work of the Serial Interface Engine.
Integrated the SIE with the USBC and Mapped the whole design to XILINX FPGA – 4000XL series – using the Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. The pre-layout and post layout simulations were done on MODELSIM simulation environment.
Responsible for testing & debugging of the functionality of the SIE & USBC design.

Ultimate – VHDL simulator conforming to IEEE VHDL specification :

Took part in the kernel development of the simulator.
Design and implemented an intermediate format for the simulator.
Wrote extensive test cases to test the various constructs and expressions of VHDL according to SPEC defined by IEEE.

References Furnished Upon Request.

Resume 2

Kenneth B. Wilson

OBJECTIVE:

Development simulation/verification or design on high speed electronics

TECHNICAL SKILLS:

VHDL, C, MTI simulator, ModelSim, RiscWatch debugger

WORK EXPERIENCE:

2000-2002
Digital Corp. San Jose, CA
Hardware Development Engineer

Modified behavioral VHDL logic of an existing PowerPC 603 cpu simulation model to communicate between an ASIC and a C code simulator, including the addition of decoders, latches, and state-machine modifications.
Designed VHDL logic code that enhanced the 603 cpu model by generating an internal address bus busy signal when an address-only phase is initiated by the ASIC.
Developed 200+ C testcases for functional simulation, system level stressing and debugging of the ASIC s internal logic, including cpu and pci address space, SRAM, cache, BAR and other registers.
Co-developed C code for parity generation on a PowerPC 603 address bus and the ASIC s read-only cache register contents.
Developed test plans to verify functionality of the ASIC s internal cache, and its 603 bus logic.
Board-level timing analysis and measurements of setup, hold, output valid times, overshoot, undershoot signal quality, frequency & voltage margining for various end-of-life replacement chips on a Fiber-channel to PCI I/O adapter board used in high-end data storage servers.

1996-1999
Simpson Communications Corp. White Lake City, UT
Hardware Development Engineer

Designed, functionally simulated, and synthesized, using PC-based ModelSim, RTL VHDL code, that converts a serial bitstream of data into bytes, then calculates the average byte value from 16 bytes of data.
Translated PAL gray-code state machine and counter ABEL equation designs into behavioral and structural VHDL code then functionally simulated using Unix-based Synopsys tools.
Translated gray-code state machine and counter state graph designs into RTL and structural VHDL code then functionally simulated, using PC-based Xilinx Foundation Series and ModelSim tools.
Developed a C code program that calculates a least-sum path of distances squared for a trade study that will implement ATM networking hardware on a RF communications data link.
Researched and wrote a white paper about Voice over ATM using AAL1 CBR, AAL2 rt-VBR & AAL5 services and implementing G.711 PCM, G.726 ADPCM, G.728 LD-CELP, and G.729 CS-ACELP ITU-T voice compression standards, for networking over a RF communications data link.

1995
Amtel Corp. Boxsboro, OR
Hardware Engineer

Configured and validated the compatibility of various PCI and EISA LANs and SCSI controllers and devices on quad Pentium-Pro Servers

ADDITIONAL JOB & EDUCATIONAL TRAINING:

Fiber Channel, ATM
VHDL course designing a 16-bit alu w/pipelined registers
Analog & RF/microwave theory, device physics theory, and CMOS VLSI design coursework
COMPASS, SPICE, Touchstone/Libra, Fortran, Mentor, Viewlogic, FPGA Express and Synopsys tools

EDUCATION:

ME Electrical Engineering, University of Utah, Salt Lake City, UT
BS Electrical Engineering, University of Utah, Salt Lake City, UT

Resume 3

George Ritchberg

MILLERVILLE, MA

OBJECTIVE:

TO PUT MY EXTENSIVE ENGINEERING SKILLS TO WORK FOR YOU

TARGET JOB: Telecommunications, Medical, Underwater Research and R & D
Target Job Title: Engineering Manager
Alternate Target Job Title: Senior Electrical Engineer

Desired Job Type: Employee, Temporary/Contract/Project
Desired Status: Full-Time
Desired Salary: 95,000.00 USD Per Year
Site Location: On-Site

Job Title: SENIOR ELECTRICAL ENGINEER/TECHNICAL/ENGINEERING MANAGER
Career Level: Management Manager/Director of Staff

Date of Availability: Immediate

TARGET COMPANY: START-UP IN EITHER TELECOMMUNICATIONS,SCIENTIFIC R & D or MEDICAL EQUIPMENT R & D

Company Size: Prefer small
Category: Electrical Engineering

TARGET LOCATIONS: Will Relocate with conditions

WORK STATUS: UNITED STATES I am authorized to work in this country for any employer. Have held Security Clearances.

Valid MASS Drivers License Class 3

PROFESSIONAL QUALIFICATIONS

MANAGEMENT SKILLS

Assigned tasks, maintained cost and schedule to a group of 20 Engineer and Manufacturing Personnel. Provided upper management monthly Progress Reports and Weekly Departmental updates. Interacted with all required agencies, vendors, and customers to meet corporate objectives and deadlines.

DESIGN ENGINEER

Extensive expertise in the Engineering Process. Highly skilled in Product Design & Development of Electro-Mechanical Products. Participated in providing Technical Engineering Leadership and Support to System, Concept, Equipment, Readiness and Production Review in Transiting “new” Designs into a Solid Product. Developed and Documented Specifications, Concept Definitions, Analyses and Trade Studies of various Electro-Mechanical Systems. Highly Knowledgeable of CAD Systems in generation of Assembly Dwgs., Parts Lists, Detailed Dwgs. Altered Item Dwgs. Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation, PWB Artwork, Mechanical Dwgs,as required.

ELECTRONIC TECHNICIAN

Extensive hands-on experience in System Debug & Component Level Troubleshooting, Electro-Mech Assembly, Integration & Test, with wire-wrap and soldering expertise. Integration and Test of a variety of Computer Hardware.

PROFESSIONAL WORK EXPERIENCE

10/2001 05/2002
SMARTWORKERS WAREHOUSE, Inc. Fitchburg, MA.
Assistant Store Manager/Customer Service Rep.

Providing management assistance to Store Manager. Responsible for opening and closing. Assignment of daily retail task and scheduling of available manpower. Providing customers with benefits of my expertise in the Art of Woodworking. Upgraded and re-merchandise entire store increasing net sales by 30 . Have sold well over 250,000 woodworking tools in 8 months

6/2001 10/2001
MILLERVILLE PHOTO PROCESSING & CAMERA, Inc. Millerville, MA.
Photo Lab Technician/Customer Service Rep.

Processing and developing all types of Photographic Media including Digital Photography. Handing of Customer questions and accountable for cash flow. Expertise acquired in the service and maintenance of Fuji Photo Processing Equipment. Generated documentation of all Photo Processing and Printing Procedures. Adhered to EPA Hazard Waste Requirements.

1/1999 12/2000
COMPUTER AIDED SYSTEMS Boston MA
Consultant Electrical Engineer/Electronic Technician

Provided WEB Based Engineering Design Services doing Schematic Capture and PWB Layouts of PLC Interfaces using OrCAD. Performed various Test Engineering activities. Involved in assessing and performing the overall Functional and In-Circuit Test activities in the production and repair of the DC-40 Handheld 486 Datacomputer w/LCD Display, PCMCIA I/F, Irda I/F, Modem I/F , and associated Power Supply SMD Assembly.

Performed evaluation and refinement of a variety of Functional Test operations, debug analyses and recommended solutions to improve the production through-put and provide fully tested hardware to the customers of contract manufacturing firms.

Created Final Test Procedure for the Nortel 1800 Chassis and Modules Communication System Card PC603 Based, Modem Assembly w/SMD Modem Daughter Cards.
Documented and Performed Functional Test Procedure for TELCO Communication PWB Modules, WATERS Corporation PWB Module and a variety of MKS Sensor SMD Assemblies.

6/1985 12/1998
ADVANCED SYSTEMS CO., Pillsbury MA
Senior Development Engineer 1992-1998

Electronic Design Laboratory Lead Engineer and Cost Account Manager. Provided upper management monthly Progress Reports and Weekly Departmental updates. Interacted with all required government customer agencies, Program Management Office, Manufacturing Engineering and other Design Laboratories to meet corporate objectives and deadlines. Managed and participated in Electrical Engineering involved in the specifying, designing, development, testing, debugging and qualifying prototype Electronic H/W.

Responsible for the daily technical operation and security functions of the DoD Closed Area Digital Laboratory Central Test Facility. Upgraded and maintained PATRIOT COMO Simulation Laboratory.
Technical Integration Lead to an engineering group of 10 engineers, in both hardware and software. Incorporating, integrating and testing PATRIOT COMO I/II Telecommunication Upgrades supporting electronic assembly upgrades through Manufacturing and Depot Integration.
Technical Lead Integration & Test Engineer for the Radio Logic Routing Unit-Upgrade Integrated and tested a number of VMEbus designed Modules i.e.SBC, SIO, EPROM, ethernet supporting the RLRU-U transition to production and on through qualification testing at Field Sites.
Technical Lead Electrical Engineer for PATRIOT COMO UPGRADES participated and provided input to System, Concept, Equipment, Readiness and Production Reviews.
Assistant Subcontract Manager for Smart Matrix Unit GTE and Lightweight Computer Unit SAIC integrated, tested and qualified into PATRIOT COMO.

Development Engineer 1990-1992

Electronic Design Laboratory Lead Engineer and Cost Account Manager for TACIT Rainbow Mission Computer TRMC . The TRMC is based upon a MC68030 with dual MC68332s along with two subsystems interface modules and a power supply. Supervised and directed four Electrical Designers.

Participated and provided Technical Engineering Support to System, Concept, Equipment, Readiness and Production Reviews transiting the TRMC Design into a solid Product with the help of Concurrent Manufacturing Engineering.

Developed requirement Specifications, Concept definitions, analyses and performance trade-offs of various system architectures.
Generated Assembly Dwgs., Parts List, Detail Dwgs., Altered Item Dwgs., Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation,PWB Artwork, PWB Mechanical Dwgs. as required.
Built, Serviced and Maintained the TACIT RAINBOW Software Development Facility, integrated prototype H/W along, with SPARC Workstations, IBM-PCs and Silicon Graphics Workstations in the performance of software code development, system simulation and software performance evaluations.
TRMC 80 Logic in Altera FPGAs
No PWB Design Errors. Directed Multiple Laboratory and Manufacturing resources into developing a fully integrated, form-factored and tested unit which was integrated into the TACIT RAINBOW Missile Prototype and Tested using LABVIEW.

Senior Electrical Engineer 1987-1990

Digital Design Laboratory Lead Engineer and Cost Account Manager. Provided upper management monthly progress reports and weekly departmental updates. Assigned design tasks and maintained cost and schedule.

Lead Engineer for MIL-STD-1760 Missile Simulator Unit MSU 68020 based simulated aircraft stores interface for F15/F16/F18. Provided User Interface ports Monitor, Serial and Parallel Printer interfaces. Tested and qualified to MIL-STD-810C 12 units.
Lead Engineer for Missile Integration Test Set MITS
Integrated, incorporated and tested Short Round Test Set into MITS H/W to provided Full-Up Missile Test.
Lead Engineer for Dynamic Software Test Facility DSTF
for software development designed, developed, integrated and tested a facility based upon five MC68020s, simulated internal missile interfaces via specialization circuitry and utilization of Personal Computers

Electrical Engineer 1986-1987

Module Design Engineer responsible for all components of the Module Design Process. Coordinated and supplied technical design input, integration test and operational inputs for innovative subsystem development.

Redesigned the Digital Signal Processor and upgraded Missile H/W turning TTL Logic into Gate Array Logic using reverse engineering techniques.
Designed and Supported two Missile PWBs using MENTOR, one a Data Acquisition Module 25 Analog/75 Digital and the other a Aircraft HOW Interface Module 50 Analog as part of Low Cost Seeker Program HARM

Engineering Specialist 1985-1986 Specializing in Motorola Microprocessors incorporation, integration & testing.

Designer for Drop Test Seeker DTS Program Zilog Z8002 based
Integrated Custom 10K Gate Arrays with Micro-Wire Technology using MENTOR and VHDL
PWB Designer of Pre-Amplifier Module 100 Analog using PSPICE and MENTOR
Proposal Engineer for US Navy Outer Air Battle Program

8/1981 6/1985
RADMEX Inc. Boston MA
Senior Electronic Design Engineer

Performed and Specified the Electrical Design, Electronic Circuit Prototyping, PWB Layout, Product Documentation, H/W Development, Integration and Testing of a Computerized Newspaper Pagination System for a start-up company. Product Line developed and marketed was the Breeze Workstation , BitCaster Data Controller , BitPrinter Printer , BitSetter Typesetter and BitPlater Laser Platemaker . Involved in all phases of electronic and product design, S/W & H/W integration, test, production implementation, field service and marketing.

Design/Developed a Raster Image Processor based upon the AMD2903 Bit-slice processor form
factored on a 12 x 12 multi-layer PWB using inverse euro-connectors.
Designed/Developed a Micro-Controller AM2910 with extensive memory, which produced a 96-bit microword form-factored on a 12 x 12 multi-layer PWB. Developed unique high-speed clock using PAL Logic. Used Future Net and Multi-wire prototyping.
Designed/Developed a Dual Port Module on a two-sided PWB using light table, which allowed the i ncorporation of a wide range of Off-the-Shelf Multibus I Modules.

9/1979 12/1980
DAYNEON COMPANY, Bedford MA
Test Engineering Aide

Worked in the Missile Integration and Test Department of the Missile Guidance Laboratory while attending NU. Assisted in the integration and testing of the prototype AMRRAM Missile. Involved in the development of a Missile Readiness Test Set MRTS . Responsibilities included: Creation of overall MRTS System Level Diagrams; Generation of Schematics, Part List and Wire Lists; Assembly Drawings. Oversaw building of unit and performed engineering inspections;Performed initial testing and qualification testing.

6/1978 6/1979
PANAMETRICS Inc., Waltham MA
Design Engineering Aide

Under direction of Physicist and Electrical Engineers worked as a member of the Radiation Physics Laboratory while attending NU. Performed tasks in Prototyping, Development and Testing of various, Satellite Subsystem H/W for GOES Program

1978-1972

Held various jobs while attending college. Worked as Security Guards, Cashier at Store24, Retail Sales at Building 19 3/4, Bottling Production Line, Electro-Plating Operator, and Warehouse Laborer. Had own summertime Painting and Landscape Business.

EDUCATION:

1981 NORTHEASTERN UNIVERSITY US-MA-BOSTON
Bachelor s Degree BS ENGINEERING TECHNOLOGY
1976 Sylvania Technical School US-MA-Waltham
Certification COMPUTER ELECTRONICS
1974 UNIVERSITY OF MASS US-MA AMHERST
Courses PSYCHOLOGY/CRIMINAL JUSTICE

MARKETABLE SKILLS

Skill Name	Skill Level	Experience
Microprocessor Design	Expert	15 years
Digital/Analog Design	Expert	25 years
VHDL/FPGA/PAL Logic	Expert	15 years
Multilayer PWBs	Expert	25 years
SMD Assemblies	Expert	10 years
EMI Design Techniques	Expert	10 years
Backplane Design	Expert	10 years
SYSTEM DEBUG	Expert	25 years
COMPONENT LEVEL DEBUG	Expert	15 years
Engineering Management	Expert	10 years
Retail Sales	Intermediate	5 years or so
Merchantizing	Intermediate	5 years or so

ADDITIONAL INFORMATION:

ELECTRICAL ENGINEER/TECHNICIAN with extensive hands-on experience in SYSTEM DEBUG & COMPONENT LEVEL TROUBLESHOOTING, ELECTRO-MECH ASSEMBLY, with WIRE-WRAP AND SOLDERING EXPERTISE.

Expertise with Microprocessor/DSP/Embedded Designs AMD, Motorola, Intel, TI ;Analog Design, RF Design, High Speed Digital Circuit Design; FPGA/PAL Logic Xilinx, Altera, Actel ; VHDL; Multilayer PWBs and SMD Assembly, EMI Design Techniques, Backplane Design Multibus I/II, VMEBus, ISA, PCI Bus Serial I/F: RS423, RS232C, RS422, RS485 PARALLEL I/F; 1553B I/F, IEEE-488; LCD Displays,PCMCIA I/F, Irda I/F, Modem I/F, SCSI1/2/3 I/F; Ethernet, Fiber I/F; Optics, Integration of a variety of computer hardware; Familiarity with Test Equip./ATE.

COMPUTER SKILLS:

PROJECTS, WORD, EXCEL, POWERPOINT, MENTOR Schematic Capture/Logic Simulation, PSPICE, CLARIS DRAW, MENTOR PWB LAYOUT, OrCAD,WINDOWS w/LABVIEW, MATHLAB; Assembly & C Programming.

Resume 4

Albert Hoover

CALIFORNIA

EMPLOYMENT/EXPERIENCE:

DIGITAL TECHNOLOGIES, San Jose, CA
1999 to Present
PRINCIPAL ENGINEER

Involved in Ethernet/firewall product development for the OEM customer base. Designed the architecture for the current ASIC Ethernet hub/switch. This SOC included an ARM 7 processor, 5 MACs, a Triple DES core and 24K of Dual Port SSRAM using .25-micron technology. Headed the design team in the implementation of the chip. VHDL was used for the design implementation. Designed the board level firewall product that uses this ASIC.

Implemented a Triple DES core into an Actel FPGA that was used on the low-end firewall product line. Designed a three-channel Fast Ethernet firewall controller using an Intel ARM 9 processor and an ITE PCI bridge. In charge of engineering development of board level designs for both product and OEM reference.

Additional engineering responsibilities include:

Wrote specifications for both chip and board level products.
Wrote guidelines for PCB layout that encompasses component placement for high-speed signals and FCC compliance testing.
Incorporated manufacturability into designs including ATE.
Developed and maintained project schedules.
Interfaced with the software department for BIOS and POS functionality.

MIRRENFAX IMAGE PRODUCTS, Sacramento, CA
December, 1997 to February, 1999
MANAGER OF ENGINEERING

Manager of the hardware engineering team. Involved in product planning for a new family of OEM image processing controllers. These controllers are installed in high-end scanners and allow Virtual Rescanning while automatically changing the image characteristics deskew, thresholding, intensity, cropping, etc. . Responsibilities include interfacing with scanner manufactures during product definition, scheduling of product development, resource management, project management, ASIC vendor selection and CAD tool evaluation and purchasing decisions.

Involved with defining the next generation Image Processing ASIC. Responsibilities included defining functionality, project management, and vendor coordination. Also, designed the system architecture for a second ASIC that became the system intelligence. This contained an embedded ARM7 processor, PCI interface, DRAM, etc. Led the design efforts on this second ASIC. Both ASICs were in the 1M to 1.5 M gate range and implemented in .25-micron technology. VHDL was used for the design implementation. Designed several controller boards that used these ASICs for different scanners.

CMD TECHNOLOGY, Sacramento, CA
June, 1995 to December, 1997
MANAGER OF ENGINEERING

Managed the Raid Division engineering team. Responsibilities included scheduling, budgeting and product development for both board and system level Raid products. Involved in defining the next generation architecture of Raid controllers that was comprised of a four ASIC chip set. Project Manager for a Digital Equipment Corp. specific Raid controller. This project was a joint effort between CMD and Digital with CMD designing the controller and Digital doing the mechanical packaging. Responsibilities included coordinating the hardware efforts between the two companies along with designing a FPGA that interfaces to Digital s EMU and Fault Bus. Designed the Raid controller board that was used by Digital. Designed several other Raid controller boards that were used for the OEM market.

Member of the Change Control Board CCB and the Advanced Products Group. Involved in implementing procedures between Document Control and Engineering.

CORSER CORP., Costa Brava, CA
May, 1992 to June, 1995
PRINCIPAL ENGINEER

Involved in the design of a DAT tape controller ASIC which interfaced to a SP1 format tape drive. This ASIC was implemented in .8-micron technology. Designed the next generation DAT tape controller ASIC. This chip was implemented in .6-micron technology and has approximately 80K gates. Designed the tape controller board that uses the new ASIC along with a Data Compression/SCSI ASIC, V50 microprocessor, 1 MB of DRAM buffering and FLASH EEPROM.

Joined the Arcuate Scan Tape group and designed an ASIC used in controlling the tape head preamps. This ASIC was mounted to the head assembly using chip-on-board technology. Also designed the Servo Gate detection ASIC used for head positioning. All ASICs designed and simulated at Conner were done using VHDL.

IRVEL CORPORATION, Scottsdale, Arizona
December, 1988 to April, 1992
MANAGER OF ENGINEERING

Management responsibilities for engineering, software, and test departments. Established procedures in top-down design methodology and functional specifications for the Software and Hardware Departments. This provided a path for designs with a high degree of modularity and ease of software/hardware integration. Defined future products and initial marketing strategies. Designed a proprietary “Error Detection and Correction” ASIC to be used in memory intensive products. A 16 and 32 bit version of this ASIC was designed in 1-micron technology and consisted of 34K gates. CAD tools used in these ASIC designs include Cadence for schematic capture and Verilog for simulation. Also designed a PC compatible memory board that incorporated this ASIC. Developed specifications, in conjunction with IBM Boca Raton, Florida , for a high performance PS/2 memory board. Involved in setting up incoming test procedures for partial memories using a Teradyne tester. Two patents emerged from the research of memory subsystems.

FUTURAMA, Sacramento, CA
October, 1984 to November, 1988
PROJECT MANAGER/SENIOR ENGINEER

Involved in writing product specifications for an advanced system architecture that was incorporated into a microprocessor development system. Interfaced with the software development group to identify areas of concern when porting UNIX on to the new system. Designed a 68000 based CPU board for this development system. During the design phase of the CPU, research was done on interfacing a 68000 to various memory management techniques along with different bus structures Multibus, IEEE 896, and VME . Designed the system protocol that provided an efficient means of communication between the CPU and intelligent, DMA driven, I/O controllers. Designed an intelligent SCSI controller that used this protocol.

TRIANON CORPORATION, Sacramento, CA
March, 1981 to October, 1984
PROJECT MANAGER/SENIOR ENGINEER

Project Manager for the Mark III minicomputer. Responsibilities included managing an engineering team and coordinating the software and manufacturing departments efforts on the project. Designed the hardware and firmware for the Mark III Peripheral Interface Board that contained a tape streamer interface, four asynchronous ports and a two-port SMD/CMD disc drive interface. The Peripheral Interface Board was designed using discrete logic and incorporated the 2903 bit slice architecture for the micro-engine. The firmware consisted of 32 bit-wide microcode.

COMPUTER AUTOMATION, Sacramento, CA
June, 1977 to March, 1981
ELECTRONIC ENGINEER

Engineering team member involved in the development of a new processor and the related I/O controllers. Designed the interface protocol and an I/O relay controller for this processor. This team was located in Dallas, Texas.

Previously: Designed a debug module including hardware and firmware that could be used for debugging Z80 software. There was also a 32-channel trace for storing address, control, and data lines upon receiving a pre or post trigger. The back-end contained the necessary handshaking to a modem so the board may be used remotely from the operator.

Initial assignments upon joining the company involved sustaining engineering hardware and firmware for a disc drive controller, synchronous communications controller, MOS memory board and static problems with CRT s.

EDUCATION:

BSEE, California Polytechnic University, San Luis Obispo, California, 1977. Concentration in Computer Systems.

PERSONAL REFERENCES:

Will be furnished on request.

Resume 5

Martin Green

Summary:

Six years of strong experience in research, analysis, design, development of instruments using VHDL/VERILOG, ASIC Design, FPGA design, digital design techniques, design using microprocessors and micro controllers. Expertise in design and simulation of electronic circuit boards using orcad, spice, circuit maker and smart work. Expertize on Active HDL simulation package.

Skills/Tools

Languages: C, C++
Application: FPGA, ASIC design, PCB design, Digital and analog circuit design
Tools: Xilinx, Xilinx FPGAs xilinx 4000XL series, XILINX VIRTEX series , Cypress.
Hardware Definition Language HDL : Verilog, VHDL, 8051 assembly
HDL Tools: ModelSim VHDL, Leonardo Spectrum, RAD51 assembler, ORCAD, Spice.
Compiler: AVC51
Operating System: Unix, Windows NT/95/98

Experience:

HITECH SYSTEMS INC. SC

Digital Automatic Moisture Computer
September 2001 – Till date

Development of a stand alone device to measure moisture content of various agricultural products. Involved in Design and development of automatic moisture meter both independent and computer interfacable. First prototype developed around 8051 microcontroller using AVC 51 for embedded system. Involved in sensor design. Design and coded same using C. Handled design and fabrication of analog and digital boards for first prototype. Second prototype being developed as full custom SOC System on chip for the calibration circuit around microcontroller 8051using simulation and synthesis tools of mentor graphics. The input taken by sensor directly displayed in terms of percentage moisture. Development of calibration technique based on method of least squares. Writing source code and test benches in VHDL for interfacing of 64K RAM, ROM, decoder and their interfacing with the A/D converter and PGA. Simulation of calibration process and verification of functionality and timing errors for same. Synthesizing code on Xilinx virtex series using Xilinx FPGA.

Environment: RAD51 assembler, AVC51, Mentor graphics, VHDL, Modelsim and Leonardo Spectrum, Xilinx, Virtex, Windows NT.

Central Scientific Instruments Organization
Dec 2000- July 2001
8 BIT Microcontroller ASIC Design Engineer

Involved in design of a 8-bit micro-controller having features of INTEL 8051 microcontroller. The FPGA consists of 128K RAM and 64k ROM and is instruction compatible to the Intel 8051.Prepared library package for the instruction set of the microcontroller in VHDL. Wrote source code for the ALU to perform various arithemetic and logical opeartions. Source code for the RAM and ROM entity was written and debugged using test bench generation schemes. A complete model of the FPGA was designed using the above logical blocks and the design was implemented on Xilinx VIRTEX FPGA. a memory mapped output port was also added to the design.

Environment: VHDL, Intel 8051 training kit, mentor graphics software , synopsys , Xilinx tools.

Central Scientific Instruments Organization
Feb 2000- Nov 2000
Microwave Oven ASIC Verification Engineer

Involved in the design of high frequency switching circuit to operate at 2.5 GHZ using spice simulation software.Involed in counter design for the programmable counter for the magnetron switching circuit. Involved in debugging, verification and analysis of critical timing parameters for low power consumption and area size using Mentor graphics Leonardo spectrum synthesis tool . Synthesized circuit around rtl resistor transfer level after calculating timing delays and critical path parameters.

Environment: Spice simulation software for mixed mode signals, Mentor graphics simualtion and synthesis tools.

Department of Science and Technology DST
July 1999- Jan 2000
Video Chip simulation ASIC Verification engineer

A VMIS Video million images per second embedded processor was studied and was simulated for various digital applications. Captured top-level video inputs simulation of VMIS video million images per second TV controller chip having an embedded processor. Enabled signal processing for digital applications. Worked in a team for simulation of chip. Carried out chip verification using using tools from mentor graphics. Verified ASIC for rtl resistor transfer logic syntax and semantics. Used Configuration Management Tool for database version control.

Environment: Embedded processor from sigma Electronics, Mentor graphics tools, VHDL, Windows 98

Technology mission for oil seeds and pulses
Sept 1998- June 1999
NIR Near Infra red BASED CEREAL / GRAIN ANALYSER Hardware engineer

Selected photodiodes according to wavelength of various samples to be measured for different parameters. The selection of photodiodes was done to opearte at radio frequencies. Designed analog and digital board around SPICE simulation software. Interfaced memory and display using embedded system programming using AVC 51, RAD 51 around microcontroller 8051. Further, an FPGA was developed to perform the application of microcontroller 8051 and the entire calibration circuit was interfaced around the Xilinx FPGA. Coded using VERILOG. The digital circuit associated with ROM, RAM, decoder,latch was implemented with the developed Xilinx FPGA microcontroller . As a team member wrote source code for the FPGA microcontroller features and tested the functionality of interfacing circuit and simulated it using modelsim VERILOG.

Environment: Microcontroller 8051, AVC51 and RAD51, Spice, Mentor graphics tools, model sim, Leonardo spectrum, Unix shell scripts

Department of Science and Technology DST
Jan 1998- July 1998
CPU Central Processing Unit Design ASIC Design Engineer

Designed and developed a 8-bit microprocessor. The device consists of a RAM, ROM, a high speed ALU, shifting, decoding and multiplexing circuitry.
Made package for the instruction set of 8085 in VHDL.
Wrote source code for the ALU to perform arithmetic and logical operations using VHDL, source code for the RAM and ROM implementation. Simulation of the functionality of the processor using test benches on Active HDL simulation package in Window NT environment. synthesized the same on XILINX FPGA.

Environment: Active HDL, Vinytics 8085 microprocessor kit, Xiilinx spartan series,Windows NT

Technology Mission of Oil seeds and Pulses
May 1997-Dec1997
Digital aflatoxin meter Test Engineer

Designed electronics related to system around ORCAD IV , checked for the functionality of the design using mixed mode signal simulation around ORCAD IV and development of calibration software around microprocessor 8085. Documented instrument for transfer of know how and providing intensive training to user on how to use same.

Environment: ORCAD IV, Vinytics 8085 kit, assembly programming for 8085.

Department of science and technology
Sept 1996- March 1997
Gold Analyzers Test Engineer

Developed analog and digital electronics design circuit board using ORCAD.
Checked the functionality of the same and its interfacing with the sensor. Documentation of instrument. Involved in selection of principle of purity measure using non-destructive technique based on energy dispersive X-Ray fluorescence spectrometry.

Environment: ORCAD Version 1V, Windows 98

The projects around VHDL were coded and tested before synthesis and also associated with PAL Programming, analog and breadboard testing. Responsible for integration and test of a UART, real time clock, keyboard controller, DMA controller and interrupt controller chip. This helped in gaining good understanding of ASIC design and verification methodologies along with PAL and FPGA programming. Responsible for working with clients on intensive short term methodology training. Responsible for training students in VHDL, synthesis and methodology. Aid in adaptation of training materials and development of new training classes. Paper publications and presentations have been made on “Digital Automatic Moisture Computer” and ” Capacitive moisture measurement of grains and oil seeds”in various national journals. Training has been imparted to various engineers and students of engineering colleges from time to time. Significant contribution in organization of various seminars and conferences related to instruments developed, various projects for water quality monitoring and soil analysis have also been designed and developed.

Education:

B.S. in Electronics Engineering.

Resume 6

Rao Shreevan

OBJECTIVE:

Assume a role in ASIC Verification/Applications/Design Engineering

PROFESSIONAL EXPERIENCE

4+ years experience in the EDA Verification Industry

Sigma Company
Jun 97 – Oct 01
Senior Project Engineer (Promoted from Applications Engineer)

Technical Lead for a TtME (Time to Market Engineering – a design verification consulting service) project for a Germany based company. Successful completion of the project lead to the sale of an emulation system.

Verified a 2+ million gate ASIC design. Assisted in project startup, Assessed project needs for verification and implemented design optimizations (for environment, RTL level and simulation). Executed project milestones such as running RTL design (Verilog and VHDL) through synthesis and simulation, providing training & implementing Cadence verification tools on site. Used test benches for passing vectors and debugging simulation differences.
Implemented Verification Flow. Identified & introduced Cadence tools to the Verification process. Advised on design methodology and validated the subsequent setup.

Lead Engineer for a European account (Philips – HDTV division): Consulted on Verification flow, and provided optimization ideas. Offered on site support and tool integration. Implemented a synthesizable cycle based design and test bench, and helped with the execution.

Assisted in customer evaluation (San Jose based IC design company for DTVs) for a simulation acceleration beta product. Worked with verification engineers to write optimized test benches.

Applications Engineer

Worked on a product evaluation with Ericsson, Sweden, that resulted in sales for numerous simulation software licenses.

Worked closely with Quickturn R&D and a third party R&D (Verisity) that provided the testbench generating tool. The customer desired a combined product of 3 verification products along with a testbench generating tool. Worked with QT and Verisity s R&D to integrate all of these products.
Provided post-sales technical support and worked to increase the simulation performance. Used profiling tools to determine simulation speed bottlenecks.

Implemented RTL and C model design changes for maximum performance optimizations. Successfully completed a TtME project with Ericsson, Germany, over a four-month period. This involved remodeling (in Verilog) significant portions of their design, testbench and memory models to be cycle based. Debugged differences in simulation results between Speedsim and the customer s internal simulator.

Successfully completed a two-month TtME project with Cabletron. Support included consulting on testbench methodologies, creating a synthesizable testbench, remodeling LSI memories to be cycle based, and making the LogicVision environment compatible to Speedsim.
Assisted the Quickturn India Distributor with a customer evaluation. Responsibilities included going on site and using test bench methods, passing vectors for showing proof of Speedsim functionality and performance on their design.
Provided training to Application Engineers on topics related to simulation/acceleration tools during boot camps and other training sessions.
Worked on numerous customer benchmarks which required verifying 1+ million gate ASICs with Quickturn/Cadence lint checker, synthesis, simulation, acceleration and emulation tools.
Presented demos and presentations at DAC 98 and DAC 00

Corporate Technical Support Specialist:

Provided technical support for all of Quickturn s Simulation/Acceleration products. Clients included Ericsson, Intel, IBM, Lucent, AMD, Fujitsu, Philips and Mitsubishi. Played a product specialist role, with responsibilities including:

Supporting Customers & Quickturn Application Engineers: coordinating and resolving software, hardware and design related issues, problems, bugs and questions.
Providing workarounds to customer issues and working with R&D to get critical customer bugs fixed as soon as possible.
Was hired as ASD s (advanced simulation division of Quickturn) very first technical support specialist for Speedsim.

ATRA Corp., Bayer Inc.
Jun 96 – Dec 96
Co-Op Internship (full time)

Modeled a MC68HC11E9 Microcontoller Unit in VHDL. The unit included microprocessor and memory components. Implemented design and verification with the help of ViewLogic tools like ViewDraw, ViewSim and ViewTrace.

EDUCATION

M.S, Electrical Engineering, University of Massachusetts, Lowell, MA Dec 96
B.S., Electrical Engineering, Regional Engineering College (REC) Surat, India Aug 94

SKILLS PROFILE

Expertise in Cadence Simulation, Acceleration and Synthesis Tools
Experienced with ViewLogic Schematic, Design and Waveform Viewer tools

EDA Tools:

Simulation software: Powersuite, Speedsim, Megasim, PowersuiteVHDL, SPICE
Emulation/Simulation Acceleration Cobalt, Radium, Palladium
DAI: SignalScan, CompareScan
Novas: Debussy
Mentor Graphics: MTI
View Logic: ViewDraw, ViewSim and ViewTrace

Languages:

Strong Verilog skills, VHDL, C, Unix, Perl

References available on request.

Resume 7

Abu Shalibdan

ASIC PHYSICAL DESIGN ENGINEER

Objective :

To achieve excellence, to be resourceful and optimistic and to pursue a challenging career in VLSI design.

Area of specialisation :

ASIC Design Flow and Methodology, Simulation, Synthesis, Floor plan, Place & Route, Timing Verification, CTS

Summary in short :

Have got more than 20 months of experience in the field of VLSI.
Worked in logical design for 8 months & rest in physical design.
Moreover i have done my academic project in VLSI field.

Professional Experience :

Arsanti! Software & Development Center(I) Pvt Ltd
Aug-2000 till date
Design Service Engineer(Physical design)
Responsiblities :

Creating various test cases & Benchmarks for customers.
Used to create testcases for QA of Avanti tools.
Creating testcases to check various releases of Avanti tools.
Clearing Customers doubts & queries regarding design & tools.

Vdesign Training & development Centre Pvt lt

Apr-2000 to Aug-2000
Trainee Design Engineer
Responsiblities :

Logical design
Digital design.
Writing Verilog codes for various small Designs.
Writing Test benches for designs.
Writing Scripts to check the designs.

Professional Training :

Undergone training on FPGA/ASIC design flow(logical design) and methodology,HDL coding for circuit implementation and test bench,simulation, timing Verification,Floorplanning,Place & Rout
(Vdesign Training & Development Centre, PondyCherry).
Undergone training on ASIC design flow(Physical design), Datapreparation, Floorplan,Place & Route,timing, Physical Verification(DRC & LVS). (Time To Market Ltd, Secunderabad).

Projects carried out: (Physical Design)

Java Processor :

Design Specification: Hierarchical design with 5 softmacros.
Technology : 0.24micron.
Goal Achived:

Hierarchial Floorplanning of Top Cell with core utilization of 75%, alongwith floorplanning of each soft macros with utilization of 80%. (Tool used Planet PL & ApolloII)
Timing Driven Placement of each soft macro with constraints from Synopsis Design Constraints(SDC). (Tool used ApolloII & Saturn)
Clock Tree Synthesis (CTS) of eachsoft macro with a target of skew of 0.2ns and phase delay 0f 2ns. The CTS is carried out for the Top Cell also. (Tool used ApolloII).
Routing of each macro and the Top Cell. (Tool used ApolloII).
Physical Verification for DRC & LVS for each macro and the Top Cell. (Tool used Hercules).

Company : TTM( as a part of training program in Physical Design)

Test Cases :

Designing of Standard Cells of 0.24 technology along with DRC & LVS check. (Tool used Enterprise & Hercules)
Die Reduction & Power Analysis : With a core utilization of 98.5%. Contains 19 hard macros, and 28k standard cells. (Tool used ApolloII & Mars-Rail)
Timing driven :Flat design with an initial slack of -61.3, and congestion overflow of 4.03%. (Tool used ApolloII & Saturn)

Bench Marks :

BenchMark For LSI logic involving diesize with 30k std cells with core utilization of 96%.
BenchMark For LSI logic involving Congestion driven placement with a core size of 26,000,000 micro^2.
Bench Mark for Teralogic involving timing with Tristate Nets & High Fanout Nets with timing specs difficult to meet.
Bench Mark for Teralogic involving Design Planning starting from synthesis to Global rout
Its mearly an analysis.

(Tools used for above BM’s: Apollo, Saturn, MilkyWay, JupiterP)

Project(Logical design) :

EIGHT-BIT MICRO CONTROLLER

DESCRIPTION: The microcontroller which is the true computer on chip.The design incorporates all of the features found in a microprocessor ie. CPU,ALU,SP,PC,genaral purpose registers and special purpose registers.It also has added the other features needed to make a complete computer ie.ROM, RAM, parallel port, serial port, counter and clk circuits Like microprocessor , microcontroller is a general purpose device but one that is meant to read data, perform limited calculation on that data and controls its environment based on these calculation.

TEAM SIZE : 7 members.
DURATION : 3 months.
MY PARTS : CPU, counter & timers, Interrupts, ROM and RAM.
TOOLS USED :

POLARIS for simulation.
EXPLORERTL for RTL analysis.

Curriculam Project :
RTL MODEL OF FOUR BIT MICROPROCESSOR :

DESCRIPTION: This four bit processor consists of the following components such as multiplexer, program counter,register,instruction decoder,ALU and timimg control,RAM and ROM .RTL code and testbench had been written for all the above units.Various stimuli had been given and the logic had been validated

TOOLS USED : simulator : MODEL SIM PE 5.3b
DURATION : JAN-2000 to APR-2000.
COMPANY : Vdesign, Pondycherry.

Exposure & Expertise:

Avant! tools	What for
MilkyWay	DataPreparation.
ApolloII	Place & Route.
Astro	Complete Design Closure Tool.
Planet-PL	Hierarchial planning
JupiterP	Synthesis & Design planning.
Saturn	Timing & VDSM Optimization.
Mars/Astro-Rail	Power & Rail Analysis.
Mars/Astro-Xtalk	X-talk Analysis.

Curriculum Details:

10th Matriculation 1993 -1994 74%
Higher Secondary 1994 -1996 81%
B E in Electronics and Communication 1996 -2000 70% (Affiliated to Madurai Kamaraj University, TamilNadu).

Skills:

Hardware languages : Verilog.
ASIC Methodologies : RTL and Behavioural.
Assembly languages : Microcontroller.
Software languages : C.
Operating Systems : Unix,Windows.
Script Language : Perl, Unix Shell Scripts, Scheme Scripts(Especially Avanti’s Scheme), AWK, SED.

Knowledge Base:

Logical Design.
Micro controller.
Microprocessor.

Key Strengths:

Time Conscious.
A go-getter.
Quest for perfection in all assignments.

Personal Details:

Date of Birth : 02-08-1977.
Language Known : Tamil, English.
Nationality : Indian.
Marital Status : Single

References : will be provided on request.

Resume 8

Eugene Freedman

Summary:

Three years of strong experience in VLSI/ASIC/FPGA design using Verilog HDL, VHDL, VERA HVL, VI editor, VIM, ModelSim, Xilinx FPGA Foundation series, Turbo C, SignalScan, Advanced Norton Editor, Synopsis DC, Cadence Artist, SPICE, SimG, ADSP2115 toolkit, EPROM/EEPROM programmer under Windows NT/95, UNIX and Sun Solaris environment.

Competency Areas:

Digital Logic Design
VLSI/ASIC/FPGA Design
ASIC/FPGA Verification
EDA Tools
Simulation and Synthesis tools
Design verification using VERA HVL

Skills/Tools:

Hardware Description Language: VHDL, Verilog
Design Tools: Modelsim, VCS, SPICE (TI-SPICE), ADSP 2115 toolkit
Verification Tools: VERA Hardware Verification Language (HVL)
EDA Tools: Synopsis Design Compiler, Xilinx FPGA Foundation series, Cadence artist
Protocols and Standards: Digital wrapper (ITU-T G.709 standard) for FEC in 10GWANPHY, SONET OC-3/3c and OC-192, PCI Bus Interface, ATM, Ethernet, Transition Minimized Differential Signalling (TMDS) for Flat Panel LCD Monitors
Languages: C, C++, PERL
Operating System: Sun Solaris 2.1, Windows NT/98/95, Unix, MS-DOS
Hardware: 10GWANPHY optical board, HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205), MPC8260

Experience:

ILNARA Networks
March 2001 – Till date
Digital Wrapper FEC (ITU-T G.709) Optical Channel Overhead Processor FPGA for 10GWAN

Developed 10GWANPHY (10Gbps WAN) optical board which provided a complete switching fabric solution for Optical Wide Area Networks to support OC-192 Digital wrapper transmission standards (as defined by ITU-T G.709). Developed architecture and coded Transport OverHead (TOH) FPGA which interfaced with HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205) devices and MPC8260 Motorola Power PC via its Local Bus. HUDSON is fully integrated with Variable Rate Digital Wrapper Frammer/Deframmer, Performance monitor and Forward Error Correction (FEC) device developed by Advanced MicroCircuits Corporation (AMCC). KHATANGA is a dense VLSI device developed by Advanced MicroCircuits Corporation (AMCC) that integrated a 10GbE MAC, a 64B/66B Physical Coding Sublayer (PCS) and a WAN Interface Sublayer (WIS) as baselined by IEEE P802.3ae task force. Used this FPGA to configure HUDSON through its microprocessor interface port, control and monitor status of Optical Channel Overhead bytes/Sonet Overhead bytes (Transport overhead and Section overhead of OC-192c frame) in data channels of HUDSON and to support all Insert/Drop Overhead Channels of HUDSON and KHATANGA.

Defined 16-bit Register Memory Map inside this FPGA with predefined memory locations for Parallel 8-bit Overhead Insert/Drop channels of HUDSON (both Encoder and Decoder sides) and for serial Insert/drop Channels of Hudson and KHATANGA. MPC8260 wrote overhead byte information into FPGA memory locations defined for those particular interfaces, which will later be inserted into insert channels on the next frame. On Drop channels FPGA collected Overhead byte information and stored them in internal predefined memory locations that will be later read by MPC8260. FPGA also monitored all status pins of HUDSON device like Loss of Clock, Out of Frame, Bit Parity Errors (BIP) and reported them to MPC8260. Implemented FPGA on Xilinx Virtex XCV200E series (FG456 package) and implemented all dual port RAMs using 28 Block RAMs available inside this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of the chip. Automated critical parts of design verification using VERA HVL. Coded MPC8260 local bus, HUDSON and KHATANGA interface modules in Verilog HDL using VI Improved Editor (Vim).

Simulated functionality using ModelSim (Modeltech_5.5). Involved in synthesis of modules using Xilinx FPGA tool.

Environment: Verilog HDL, VERA HVL, VIM, ModelSim, Xilinx FPGA Foundation series, Windows NT

Contesse Semiconductor Corporation
October 2000 – February 2001
SONET Transport Overhead Processor FPGA (OHP155)

Designed an FPGA as part of GigaStream Switch fabric chipset for collecting and transmitting overhead bytes (both Transport overhead and Path overhead of SONET OC-3/3c frame) to/from optical interface. Developed architecture and coding of SONET Over Head Processing (OHP) FPGA interfaced with Spectra155 interface, High Capacity Multi-Vendor Integration Protocol interface (HMVIP) and CPU interface. Spectra interface consists of Transport OverHead (TOH) and Path OverHead (POH) interfaces to transmit and receive directions from Spectra chip. Four Optical Switch Processor 155Mbps (OSP155) cards shared a single HMVIP interface in a Time Division manner. The CPU interface is a Network Switching Processor (NSP) CPU interface to OHP FPGA for configuring. TOH/POH overhead byte information collected on HMVIP side is sent to corresponding Spectra155 devices. Similarly overhead data that is sent by Spectra155 device is sent to HMVIP interface in correct time slot at correct frame location.

There are eight dual port asynchronous RAMs implemented in this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of chip. Coded transmit side modules of this architecture in Verilog HDL and tested functionality and performance. Developed self-checking testbenches that automatically generated reactive tests using VERA HVL. Used Xilinx synthesis tool for synthesis of design and generating sdf file. Did post-synthesis simulation of this design.

Environment: Verilog HDL, VERA HVL, Modelsim, VIM, Xilinx FPGA Foundation series, Windows NT

Contesse semiconductor Corporation
April 2000 – September 2000
Candela FPGA

Designed an FPGA to convert Fusion Omni-Connection for Universal Switching (FOCUS) bus interface to Packet on SONET physical interface (POS_PHY) bus interface, so that Vitesse s VSC9112 (OC-48) chip could be interfaced to Vitesse s Network Processor IQ2000 through this FPGA chip. Designed in Xilinx Virtex-E XCV-300E FPGA. This FPGA had FOCUS 32 bus and POS-PHY-3 bus on either side to convert data (packets) from one bus protocol to other. Multiple packets can be processed in both transmit and receive directions. Used two FIFOs in Ping-Pong mode to carry Fcells in both receiver and transmit side. Did regression testing of Verilog RTL code. Generated random set of valid test cases using a seed value. Used Turbo C for writing a C code, which automatically selected a random number of test cases from the valid testcase library using a seed value.

Environment: Turbo C, Verilog HDL ModelSim, SignalScan, VIM, Windows NT

Creative Instruments
December 1999 – March 2000
Timing Controller Chip with mini-LVDS and FlatLink

Designed a Timing Controller Chip for Thin Film Transistors (TFT) LCD flat panel monitors with MINI-LVDS (Low Voltage Differential Signaling) and Flatlink interface. This chip id designed for customers like IBM, Samsung, LG with programmable display resolutions ranging from XGA to UXGA and to even support SXGA+ and W-UXGA. Chip interfaces with CPU display card using TMDS (Transition Minimized Differential Signaling) Flatlink standard for digital transmission of Video output data at 1.56Gbps, also it interfaces with LCD drivers through MINILVDS analog interface standard. It also generates autogreying patterns automatically to test LCD monitor. Involved in digital architecture design of chip. Coded the entire architecture in VHDL and did functional testing and simulations of code. Used Shell Scripts for taking test bench (testing file used to test functionality of VHDL code). Used Synopsis DC for synthesis.

Performed post-synthesis simulations. Tested and verified actual performance of chip on LG s LCD monitor.

Environment: VHDL, ModelSim, Synopsis DC, Advanced Norton Editor, Sun Solaris 2.1

Creative Instruments
May 1999 – November 1999
Design of Flying Adder Digital Logic for PLL (TFP8501) Chip

Designed a Scaler chip for LCD flat panel monitors to support resolutions upto SXGA+/UXGA and to maintain compatibility of various video cards and LCD monitor resolutions by upscaling or downscaling resolutions whenever required.

Involved in design of Digital logic for Flying Adder PLL (50MHz to 350MHz).

Did coding of digital logic in VHDL. Performed synthesis of design using Synopsis DC. Used SPICE for analysis the analog behaviour of timing critical nets. Interfaced logic with analog PLL using SPICE.

Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, TI-SPICE, Sun Solaris 2.1

Creative Instruments
January 1999 – April 1999
Design of Analog PLL

Involved in the design of a TMDS receiver chip with HDCP for LCD flat panel monitor to support Transition Minimised Data Signaling protocol with High Data Content Protection. Rate of video data transfer on TMDS channel is 1.6Gbps.

It enabled data interaction between CPU monitor video card and LCD monitors to be entirely digital. Designed architecture of Analog PLL (65MHz to 250MHz).

Did Analog circuit design of Phase Frequency Detector (PFD), Charge Pump, Bias Generator and VCO. Used Cadence Artist and Spice for analog design.

Carried out all process corner simulations of individual design modules and completed closed loop simulations of PLL.

Environment: Cadence Artist, SPICE, SimG, Sun Solaris 2.1

Creative Instruments
October 1998 – December 1998
Power Management Module for TFP401 Chip

Involved in the Design of a TMDS receiver core chip for LCD monitors. It supports Transition minimized Data Signaling protocol from PC Video cards to LCD monitor. Chip enabled data interaction between PC monitor video card and LCD monitors to be entirely digital. Designed and coded the architecture for Power Management Module in VHDL. Did synthesis of this module.

Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, Sun Solaris 2.1

Mignion Systems Limited
July 1998 – September 1998
Design of Single Phase Energy Meter

Designed and developed an Energy Meter architecture using ADSP2115 digital signal processor that calculates voltage, current, power, power factor, frequency and does harmonic analysis. Did assembly language programming of design.

Successfully tested design on power lines.

Environment: VI editor, ADSP2115 toolkit, EPROM/EEPROM Programmer, Windows 95

Education:

M. S. in Microelectronics and VLSI Design.

Resume 9

Ragha Sheen

Sunnyvale, CA

OBJECTIVE:

ASIC/FPGA Design & Verification Engineer

QUALIFICATION :

2.6 years of experience in FPGA Design & ASIC Verification.

SKILLS :

Proficient with coding RTL & Behavioral using Verilog and VHDL.
Proficient with developing test environment for functional verification.
Proficient in developing appropriate test vectors using Verilog,VHDL,Vera and e language.
Proficient in writing fully automated test benches.
Experience with synthesis and optimization of Verilog/VHDL code
Experience with FPGA implementation with Xilinx.
Worked on Mentor Graphics Synthesis tool – Leonardo Spectrum, Synplicity Synthesis tool Synplify
Worked on different simulator tools- Verilog-XL(Cadence), Modelsim(Modeltech) and VCS(Synopsys).
Worked on Mentor Graphics Schematic Entry Tool – Design Architect.
Worked on PCI 32 bit @33Mhz
Worked with Specman, an ASIC Verification tool from Verisity
Familiar with Vera, an ASIC Verification tool from Synopsys
Familiar with DSL Protocol.
Familiar with ATM Protocol.
Familiar with AMBA Bus Architecture.
Familiar with 8085 and 8086 Architecture.
Familiar with 8085 Assembly Language.
Familiar with software languages C and Fortran.
Good communication skills

WORK EXPERIENCE:

11.2000 – Present
ABC Chips Inc, San Jose, California
FPGA Design & Verification Engineer

Name of Project: Network Processor Verification

Role :

Wrote test plan for one of the modules in the chip.
Developed the test bench for the module.
Wrote test cases in Verilog.
Developed the different interfaces around the module.

System Description

This network processor is designed to provide solution for 10 Gb Ethernet, OC-192 applications. The ingress device supports a POSPHY Level 4 (PL4 ) interface and the egress device supports CSIX interface to a switch fabric.

Tools Used : VCS & Modelsim
Language Used : Verilog

Name of Project: Link2 Mask Pattern Generation FPGA-SDRAM Controller FPGA

Role :

Designed and Synthesized SWATH cycle Controller module.
RTL coding done in Verilog with Verilog-XL and Synthesized using Synplify
Developed the different interfaces around the Link 2 FPGA.
Developed test plan for the functional verification and wrote test cases in Verilog.
Done the module level verifications and top-level verification.
Reported bugs and worked with the design team in fixing the bugs.

System Description

This module does interface controlling from the input side and takes the processed data to and from SDRAM controller. This module also does the interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA. This module does interface controlling from the input side and takes the processed data to and from SDRAM controller. This module also does the interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA.

Tools Used : Verilog-XL (Simulator),Synplicity (Synthesis tool).
Language Used : Verilog

07.2000-11.2000
Silicon Grafic Systems, Bangalore, INDIA
IC Design Engineer

Name of Project: Rrishti-1-Trace Receiver ASIC Verification

Role :

Handled the responsibility of verification of all NRT transfers using IBM(Internal Bulk Memory) at module level and device level.
Wrote test cases in ‘e’ language and verified them using Modelsim simulator.
Reported several bugs in the design and worked with the designers to fix those bugs.

System Description

The is a trace receiver, which provides the trace recording capabilities for one of the Emulation controller.

Key features

The key features of the trace system ASIC are:

Provides a maximum of 4 channels operated at single edge clocking (positive edge, negative edge, positive edge and negative edge, or alternatively 2 channels operated with Bi-phase clocking scheme.
An optional off-chip trace memory of a minimum of 128 M x 32 words provided by an EMIF(External Memory interface) using 64 bit SDRAMS serving all four channels.
On-chip trace static RAM memory organized as 32k x 64 (ie.256 bytes) serving all four channels. This memory is used as channel temporary buffers and scratch memory when SDRAM is used to store channel data.
trace packet width from 1 to 20 bits
167 MHz processing rate

Detailed Description:

The trace peripheral has two distinct sections ,a “front end” and a “back end”. The front end (TPFE)acquires the trace data presented by the target and packs this data efficiently into 64-bit words. The Trace peripheral back end (TPBE) dispositions this data to trace memory, managing buffer locations, lengths, and host access to these buffers independent of whether the storing process is active. In short, the TPFE contains the acquisition, packing and buffering functions while the TPBE distributes the TPFE generated data into Trace buffers.

Tools Used: Modelsim (Simulator),Specman Elite (ASIC Verification tool).
Language used : VHDL (RTL), e language for test cases.

05.1999 – 07.2000
Engineering Design Center , Bangalore, INDIA.
Hardware Design Engineer

Name of Project : PCI based high speed data acquisition card for signal Processing

Role :

Designed the Hardware .
Designed the FPGA& CPLD .
Done the functional simulation & synthesis.
Done extensive timing simulation with back annotating the sdf.
Done schematic Entry using Mentor Graphics Tool.

System Description

PCI Add on card with PLX 9080 as PCI Bridge and on the local side uses one FPGA , which does all logic including bus arbitration and data transfer to FIFO . It actually acts as a local processor to PLX 9080. The input to the card includes 16-bit parallel data stream with strobe and 100 Mbps serial streams. Only one of these may be activated at a given time.

The design goal is to accept data rate upto 40MB/s, but the testing will be limited to 20 MB/s transfer to memory.

FPGA we were using was Spartan series XCS 40-4 ns. VHDL entry, compilation and functional simulation is done through Model SIM a front-end tool, then after this we had done synthesis through Leonardo spectrum. From that some edf(edif) files are generated and we open those files in the Xilinx tool. We are using Xilinx tool as the back end. Here we place and route the design and generate timing simulation data. From there one sdf(standard delay format) file is generated. This includes all the internal delays of the device. The Xilinx tool also generates a test bench file. We will apply our stimulus to that Test bench and we make that as the test bench for timing simulation. So when timing simulation comes we load our design file and the sdf file and simulate.

Usually the FPGA has to be configured using a serial EPROM. But in our case since the FPGA is being configured from the system side, it cannot be a permanent data as from EPROM. So we are using the CPLD to configure the FPGA. It will take data through the local bus and load it to the FPGA.

Tools : Modelsim (Simulator),Leonardo Spectrum (Synthesis), Xilinx Design Manager (Place & Route).
Language : VHDL

12.1998 – 04.1999
B.Tech Final Year Project done at ER & DCI , Tvm, Kerala, INDIA

Project Title: VHDL Model of UART

Role :

Developed the architecture
Designed and done RTL coding in VHDL.
Done the functional simulation, synthesis and mapped to the target PLD

Tool Used : WARP 4.1
Simulator used : NOVA
Host Platform : PC under Win95
Device Mapped : CY7C341 from Cypress ( 192 Macrocell EPLD)

Project Objectives:

Study in detail one Standard HDL
Study in detail about the PLDs
Write own HDL code to build a model of one Standard UART chip with defined requirements
Simulate the code for functional verification
Synthesize and map the design to a suitable PLD.

EDUCATION :

10.1995 – 05.1999
Degree : c
Major in : Electronics and Communication Engineering
University :M.G University Kerala, INDIA .

HONORS :

Got an award from Silicon Automation Systems ,BANGALORE for being the best project team for the quarter of the year 2000 for the Rrishti-1 Project.
Got an award from the customer( Texas Instruments,Bangalore) for outstanding Performance & valuable contribution to the verification of Rrishti-1.

Higher Education :

Doing part-time courses in San Jose University for
Course 1- Advanced Logic Design (Winter 2001)
Course2-VLSI Design I (Winter 2001).
Course3-Logic Design using HDL- Project- Bluetooth Transmitter
Course4-Logic Synthesis- Done using Synopsys DC

REFERENCES : Can be provided based on request

Resume 10

Ravi Saharan

Sunnyvale, CA

Objective

Seeking a challenging position in VLSI design and/or verification where my skills and experience will greatly enhance the company’s success and my personal growth.

Skills

H/W Description Languages: VHDL, Verilog.
Place and Route: Lucent OFCC (ORCA Foundry Control Center), Altera Quartus, Xilinx Alliance.
Synthesis: Exemplar logic (Leonardo Spectrum).
Simulation: Modelsim, Quicksim from Mentor Graphics, VCS from Synopsys, VirSim (graphical user interface to VCS for debugging and viewing waveforms).
Others: Mentor Graphics DA, Autologic II, Visual HDL, Renoir.
Languages: C, C++, perl, Unix Internals like Shell and Awk.
Operating Systems: Solaris 5.6, FreeBSD 2.2.6, Windows NT/98.
Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF
Others: PCI.
Revision Control: CVS.

EXPERIENCE

Saristos Logic Corporation, Mountain View, CA
3/2001 – Present
Consultant, ASIC Engineer

As an ASIC Engineer, was a key individual contributor on a team responsible for conceiving, planning and implementing software and hardware systems required to validate Storage Area Network (SAN) systems. Storage Area Network (SAN) offers simplified storage management, scalability, flexibility, availability, and improved data access, movement, and backup.

Worked closely with the ASIC and hardware development teams with the goal of delivering quality ASIC silicon for advanced storage.

Responsibilities:

Register/memory access via PCI cycles or PCI DMA transfers or RTL hierarchy.
Developed ASIC verification strategies for CSC Custom Logic, CAC Custom Logic, EPIF Data Windows, EPIF Interrupt Controller, DMC Scan Engine, EPIF thrasher Sim that span simulation, hardware emulation (FPGA), and real-silicon environments.
Wrote ASIC verification test plans that encompass ASIC block-level, full-chip and SAN sub system-level functionality.
Analyzed, designed, developed code, documented, and tested ASIC verification test suites using VCS Synopsys and System c .
Migrated test suites developed in the Verilog simulation environment to both hardware emulation and final silicon lab verification environment.
Each Verification Sim was tested with a model which also takes the same input vectors and generates expected value for that input vectors. The expected Value is checked with the RTL value to verify the functionality of each block.
Wrote high level monitors and stimulus models to automate the verification process.
Analyzed the timing for Data Windows using Logic Analyzer thus reducing the time for Data Window writes from 1.5 hrs to 18 mins for 1GB of memory on Hardware Emulation Platform.
Wrote Scripts for HEP (Hardware Emulation Platform) regression suites.
Participated in estimating verification development schedules and ensured on time delivery.

Infotech Systems Inc., Boston, MA
1/2000 – 3/2001
Design Engineer

As a Design Engineer was responsible for conceiving, designing, developing and testing digital circuits for both ASIC and FPGA. Designed and tested the digital portion of the chip for television.

Responsibilities:

Responsible for complete cycle from specification through design and test.
Designed the digital circuit using VHDL.
Synthesized using Leonardo Spectrum, targeting it to Lucent’s ORCA series FPGA.
Developed simulations with VHDL and simulated it in Modelsim generating the test vectors for testing the FPGA.
Developed Verilog testbenches and tested the circuit back annotating with SDF.
Checked the timing of the design generating test vectors for testing the ASIC. Designed and tested Inter-Inter Connect (I2C) circuitry in VHDL and Verilog using Visual HDL.
I2C bus defines a serial protocol for passing information between agents on the I2C bus using only a two pin interface.
Designed a I2C bus slave interface controller using Visual HDL.
Synthesized the circuit using Leonardo Spectrum and targeted to Lucent’s ORCA series FPGA.
Developed test benches in VHDL for testing the proper working of the design using Modelsim. Designed and tested the read channel chip.
Worked on three different versions of the read channel.
Designed the FPGA using Visual HDL generating the RTL for the design.
Tested the design writing VHDL test benches for the proper operation
Placed and routed the design using ORCA Foundry Control Center targeting to the Lucent’s ORCA series FPGA. Evaluated place and route tools for the read channel chip.
Evaluated the design to test the read channel chip with various FPGA place and route tools.
Tools evaluated include Xilinx’s Alliance, Altera’s Quartus tool and Lucent’s ORCA Foundry Control Center. Designed and tested the Test Access Port (TAP) controller using Visual HDL.
Designed an IEEE standard TAP controller.
Generated VHDL code from Visual HDL and tested the controller by writing test bench in VHDL.
Simulated it using Modelsim. Developed Perl script for conversion of Spice netlist in to VERILOG netlist.
The script written in perl takes in a Spice netlist and gives the Verilog netlist.
Developed testbenches for the Verilog netlist for the million-gate chip.
Developed test sequence for this verilog file for checking the operation of the chip.

Education

Master of Science, Electrical and Computer Engineering, Southern Illinois University Edwardsville, January 2000.
GPA: 3.727/4.0.

Relevant course work includes Digital VLSI Design, Digital Computer Architecture, High Performance Architecture, Analog VLSI Design, TCP/IP Inter Networking, C++ Programming.

Master’s Project

Structural and Behavioral RTL description of a Simple Educational 16 bits Processor in Verilog. The structural description of the data unit, the control unit, SRAM and other modules were coded and tested. Other Projects
Design of a Linear Interpolation Filter using Verilog and full custom IC layout.
Design of a Simple Educational Processor using VHDL.
Designed and simulated a sigmadelta modulator for an EEG IC.

Bachelor of Engineering, Electrical and Electronics Engineering, University of Madras, May 1998.
GPA: 80.5%

Reference: Furnished upon request.

Resume 11

Kumar Ravish

ASIC-FPGA Design & Verification Engineer

Objective

To work where I am given the opportunity to assionately exploit my knowledge to the fullest level of satisfaction both personally as well as for the company I serve on the whole.

SUMMARY OF EXPERIENCE:

Over 7+ years of experience 5+ years of experience in Hardware Design, Development & Verification using ASIC, PLD, CPLD & FPGA Designing & Verification, Board simulation, ANSI C, Assembly, C++, PLI, PCI, VLSI, PCB, Verilog, Synopsis, VHDL,VERA, Gigabit Ethernet,(Networking) SONET,ATM, Device Drivers , Win Board, Synthesis, Verification of Design.CMOS,Embedded System (SOC),Real Time Operating System RTOS), VxWorks, Logic Analyzer, Simulator, Emulator & Programming of RAM(SRAM & DRAM) With excellent analytical and programming skills. Very conversant in documentation, presenting prototypes, client interaction, quality assurance. Good communication and interpersonal skills. Strong Points include quicker grasp to new concepts, the ability to pursue matters in great detail and able to work in a team.

Education:

Bachelor of Electrical Engineering from Bangalore University.

Employment history:

Jan 2000 – Present DSSABC Software, Inc., CA, USA
Feb 1998 – Nov 1999 FDD Containers Limited, London, UK
Oct 1996 – Jan 1998 RANDY ENGINEERING, Tripoli, Libya
Jul 1994 – Sep 1996 Advanced Systems & Solutions, Delhi, India

Professional Experience:

Client: Smart Networks Utilties, Santa Clara, CA Aug 2000 to Present.

Scope of the project was to design & develop a micro controller chip for networking purpose on networking boards, which sends and receives data digitally & Supports Gigabit Ethernet on Fiber Optics.

My Role: As a team member I was involved in

FPGA & ASIC design
Wrote verilog HDL code for design.
Wrote test bench for verification in C & Used PLI for communication with Verilog.
Integration testing & verification.
Functional testing & verification.

Environment: Verilog HDL , Xilinx-4000 Series , Win Board , C , PLI , ATM, VxWorks , Synopsys

Client: Digital Design, Santa Clara, CA Jan 2000 to Aug 2000

The objective of this project was to design, developed the data networking boards and test benches for verification purpose of pre written functions in verilog .

My Role:

Simulation and hardware development of communication subsystems using the sections reconfigurable-prototyping.
Design, simulate, and test digital hardware.
Developed data networking boards, and backplanes.
Performed the design, capture the schematics and oversee the board layout.
Performed board simulation and signal integrity

Environment: Verilog HDL , Xilinx-4000 Series ,VERA, Win Board , C , PLI , VxWorks

FDD Containers Limited, London, UK [Feb 1998 – Nov 1999]

Project: DSP Motion Controller 09/98 to 11/99
Client: FDD Container (UK)

The purpose of the project was to design and develop micro controller chip 80188EB for controlling the motion of Mechanical Equipment Boomer there was servo motors which controls Boomer Motion.Servo Motor was controlled by the tech called DSP motioncontroll (Digital Signal Processing). The RTOS was designed & implemented on higher priority algorithm, the signals of higher priority is served earlier than a signal with lower priority. The code was written in c & inline Assembly on Host Computer.

My Role:

Design, simulate, and test.
Programming of SRAM & DRAM.
Writing Test Benches for Verification in verilog & C.
Performed board simulation

Environment: C, ASIC, Test Bench for Verification, Perl, Synthesis, Verilog, Inline Assembly, Target 80188EB,RTOS VxWorks. Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer.

Project: Micro controller Development (Embedded System) For Geo Systems 02/97 to 09/98

The purpose of the project was to design and develop micro controller chip 8051EB for controlling heat Generation in Turbines of thermo electric Power plant. The processor controls the steam temperature. Which receives the signals from Boiler sensors. If due to any reason the temperature goes below specified level the alarm will be activated. It had the provision of printing the Time versus heat graph controlled by the processor 24/7.Programming of the RAM was done by c & inline assembly. Device programmer was used to copy the image files on the chip.

My Role:

Design, simulate, and test micro controller chip.
Programmed SRAM & DRAM.
Wrote verification code in verilog & C
Performed the design, capture the schematics and oversee the board layout.
Performed board simulation

Environment: ASIC Design, VHDL, Verification, Test Bench, C, PLI, Inline Assembly, Perl, Target 8051, RTOS PSOS, Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer.

RANDY ENGINEERING Tripoli, Libya [Oct 96 – Jan 97]

Project: Material Management System 10/96 to 01/97

DOS based Stand alone Database Application developed under C++ for Civil Engineers providing Menu Driven User Interface for calculating the Quantities of material required and its Costing, providing an easy access to feed the User input data. Its related Quantity and Cost will be calculated automatically with the help of in-build functions & related data Information that is also capable of modifying as per the user specifications and standards. It takes the Complete Details of a building (to be constructed) by providing an Interface and Calculates the quantity of material required with its estimated cost, as per the standards specified. It provides an easy access for modifications.

Environment: C, UNIX and MS DOS.

Smart Systems & Solutions, Delhi, India [Jul 1994 – Sep 1996]

Project: Employee Scheduler Management Jan 96 – Sep 96

A standalone Application developed using Visual C++ 5.0, for Microsoft Windows95 and Microsoft Windows NT, to be used as the Employees Schedule and its Related Information, in a Large Companies, Hospitals etc. Developed system allows you to get detailed Information with Graphical Representation related to an employee and its Schedule (Working and Leave Duration’s Designed for a Complete year) Allows Online Modifications for Updating the Individual Schedule of an employee, and its related information. Which intern Automatically updates the related Schedules of other employees if desired.

Environment: Visual C++, MS Windows 95.

Project: Management and Security of File System Feb 95 – Jan 96

An Application Program of which the Core Part is handled using C++, and the GUI (Graphical User Interface) is handled using Visual C++ for Microsoft Windows 95 and Microsoft Windows NT. Which allows the user to maintain its File System with Security, providing File and Application Locking. With which it is possible to lock any Executable Program from being unauthorized Access, by providing Password facility.

It is Capable of Locking Windows95 from being Loaded Unauthorized at the Boot time.
Provides an Easy and Quick File Search.
Provides Quick Access to file Opening and Executing.
Provides File Viewing facility before editing the files, giving an Easy access to Editing.

Environment: Turbo C++ 3.0, Visual C++ 5.0, and MS Windows 95.

Project: Standard Product “Impress” Jul 94 – Feb 95

“Impress” is a standard integrated package targeted at the Printing and Advertising Companies as the major customers. It was designed and developed by Thomson Technologies, India. The product included modules such as Financial Accounting, Purchase, Sales, Inventory and Production (Studio Section & Camera Section). Was a member of the team, which designed the system? Other responsibilities included coding and testing. Developed 12 forms and various other Reports.

Environment: Visual C++, Visual Basic, MS Windows 3.1

Visa Status : H1B

References: Available on request

Resume 12

Vijay Harishini

Sunnyvale, CA

Summary:

Nine and a half years of strong experience in Verification of ASICs using Verilog, VHDL, VERA, Verilog -XL, Synopsis VCS, Mentor Graphics Co-Verification Environment, Assembly Language on Unix platform. Expertise in writing Verilog Model, developing test plans, Quick test writing and setting up Verification environment in Verilog/VHDL. Good knowledge of PCI protocol.

Skills:

Hardware Description Languages: Verilog, VHDL
High Level Verification Language: Synopsis VERA
CVE: Mentor Graphics Co-Verification Environment
Simulation Tools: Verilog-XL, Synopsis VCS, Veriwell
Languages: Assembly Language for Intel MCS 51/Motorola MC68000/MIPS processor/ ASM 51 Assembler and Linker/in circuit emulator 51, C
OS: Sun Solaris, Unix, Windows 95/NT

Experience:

LSX Technology, Inc., Moutain View, CA
August 01 till date
Verification of PCI bridge( PCI to local) PCI 9656

Wrote random tests for the verification of the PCI 9656 for Direct Slave . Direct Slave means that the chip is the slave on the PCI bus, Direct master means that the chip is the master on the PCI bus. Worked on PCI compliance testing for the PCI 9656 using Synopsys PCI compliance suite. Worked on FIFO testing. There were 2 FIFOs. One for the Direct slave read and the other for the direct slave write. Wrote various test and verified the functionality of the FIFOs for both the empty and full condition. There were numerous condition to fill and empty the FIFO. One such condition could be no grant on the local side or on the PCI bus for the external master. The chip has 3 modes namely M, C and J modes . These modes are the local bus types. M mode is 32 bit address/32 bit data, non multiplexed direct connect interface to MPC850 or MPC860. C mode is 32bit address /32 bit data non multiplexed for intel processor i960 and J mode is 32 bit address/32 bit data multiplexed.

Environment: Verilog, Sun Solaris

Visitor Graphics Corporation, CA
January 01 – till date
Field Application Engineer

Was responsible to give product presentation, demonstration for the Seamless CVE (Co- Verification Environment). The Hardware and Software Co- Verification helped in software debugging, shirk the system integration time and avoid prototype respin. Was required to perform evaluation of the product at the customer site. Satisfied the customer about the utility of the product through a question/answer session and with follow up visits to potential customers. Performed evaluation of the product and against the product of competitors.

Environment: Verilog, CVE, Assembly, Sun Solaris 2.x

Advanced Networks, CA
December 99 – December 00
Verification of a Packet Classification ASIC

The ASIC was used to offload the network processor of the job of classification of the packet. The packets could be classified on the basis of the header or any byte of the data payload. The ASIC had system bus interface, ERAM interface, AOC PIB modules.

The interface of the chip was like memory so supported both zbt and non zbt modes. The system bus could be configured as 64 bit or 32 bits. The speed of the ASIC was in the range of 50 – 100 MHz. Wrote diagnostics to verify the system bus interface using Verilog. Build the Chip Verification Environment using VERA. Debugged the failing test cases. Found several bugs and fixed the bugs.

Environment: Verilog, VERA, VCS, Sun Solaris 2.x

VASHIBA, CA
June 99 – November 99
Verification of a Networking SOC

Involved in Verification of a Networking SOC having MIPS Processor, SDRAM Memory, MAC, PCI and HDLC. Was responsible for Verification of the bridge between the MIPS Processor and the Toshiba Proprietary bus using Assembly and Verilog in a multi master System Verification environment. Developed several MIPS Assembly and Verilog based test to verify the functionality of the G bridge and HDLC. Translated the unit level test cases for HDLC to system level tests. Verified the tests at full chip level. Found bugs, notified the designer and suggested fixes.

Environment: Verilog, Assembly, VCS, Unix

ABISCO, CA
January 99 – May 99
Verification of a Network Output Controller

Network Output Controller was responsible for moving data (packet) from the packet buffer (external SRAM memory) through the port FIFO s to the network interface. Verified the above functionality of the NOC by writing the functional models in Verilog. Verified functional models. Verified Packet buffer read and writing. Packet buffer was read and written as 1024 bits at a time in 11 clock cycles. Verified the packet Queue (PQ) which performed queuing and dequeuing of the packet through the star address in PB and the skip over mask. Verified Packet Receiver which received packets from all the 50 ports at the network interface in the TDM manner. Functional model of the NOC was written before the RTL could be plugged with other functional models. RTL replaced the NOC model. Developed the test bench and wrote task for specific functionality. Developed test plans, test cases for the Chip Level Verification of the ASIC using Verilog. Found and fixed bugs.

Environment: Verilog, Verilog -XL, Sun Solaris 2.x

HIPRO, CA
March 98 – December 98
Design and Verification of HDLC Controller (Project Lead)

Involved in Design and Verification of HDLC Controller with a generic 8- bit microprocessor interface. The HDLC controller framed according to the HDLC protocol. The frame checksum generator and checker were implemented. The controller was to the ITU Q 921 specification. Designed the HDLC controller. Involved in portioning of the design into Transmitter and Receiver. Verified the HDLC. Synthesized the HDLC.

Environment: Verilog, Verilog-XL, Sun Solaris 2.x

Sonet Technologies Pvt Limited
January 97 – February 98
Development of VITAL ASIC Libraries

Verilog to VITAL converter was used to translate the Verilog Structural Model to VITAL. Testing was done on Quick HDL simulator, which was one of the sign off simulator for LSI logic. Was responsible for Conversion and Simulation.

Environment: VHDL, Quick HDL, Unix

Sonet Technologies Pvt Ltd
April 95 – December 96
Development of Test Bench for BUS Interface Model for MC68030 and MC68020

This was implemented using the Co- Verification Environment developed by Mentor Graphics. The hardware (Verilog/VHDL) was simulated on HDL simulator like QuickHDL and the software was simulated on the software simulator (different for each processor). The Bus Interface Model was specific to the processor and generated bus related cycles for the processor depending on the type of access. The tool was used in designing embedded system where the software could be verified against the hardware before the hardware prototype was made.

Environment: Verilog, VHDL, CVE for Mentor Graphics, Unix

Parametric Network Limited
November 91 – March 95
Development and Verification of a Keyboard Controller using 87C51FA Microcontroller

Developed assembly language programs. The keyboard and the system (486 PC) serial communication was established and keys were scanned. Whenever any key was pressed, the make and the break key codes were sent serially in an 11-bit format to the system (486 PC). Provision was made for interfacing more than 1 keyboard with this keyboard controller. This also included the standard PC keyboard.

Environment: Assembly, Unix

Resume 13

Ramesh Ravisare

OBJECTIVE

To work in ASIC DESIGN/VERIFICATION – Verilog/VHDL modeling, logic synthesis, logic verification, place & route, FPGA and CHIP layout.

EXPERIENCE SUMMARY

VLSI Logic design – Complete design flow from RTL to layout.
Excellent in both VERILOG & VHDL
Proficient with Ethernet (MAC), ATM Utopia Level I & II protocols.
Complete understanding in architectures of PCI & OHCI.
Proficient with USB.
Knowledge in Unix, Perl and ‘C’.
Knowledge in VERILOG PLI CONCEPTS.
Good experience in Digital synthesis and Place & Route.
Configuring CPLD with bit blaster using MAX+plus II.
Expertise in Altera /APEX FPGA.
Experience in Assembly Language.
Analyzed circuits using SPICE.

TOOLS USED

Simulation : Verilog XL from Cadence 2.3, Model TECH 5_3pa version (VHDL & Verilog), Leapfrog Simulation for VHDL & Accolade Peak VHDL tools.
Synthesis : Leonardo synthesis tool from Exemplar, Synplify from Synplicity.
P & R : Altera MAX+plusII , Lucent , Quarters Tool for APEX Devices. Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics.
Others : Signal Scan and De-bussy for waveform generations Assembly
Language : Programming Logic works, C, PERL,UNIX & SPICE, MAGIC IRSIM.
‘C’ Compiler : Green Hills Software

WORK PROFILE

Company I : Analog Systems, CA.
Duration : Jan ’00 – Till Date
Designation : Member Of Technical Staff

Company II : Trenton Chip Devices, Inc., CA
Duration : May ’99 – Dec ’99
Designation : VLSI Design Engineer

Company III : Trenton Chip Devices, India
Duration : May ’97 – Apr ’99
Designation : VLSI Design Engineer

EXPERIENCE

Profile I :

Company : Analog Systems , Inc.
Location : Santa Monica, CA
Designation : Member Of Technical Staff.

Project : AD 6489 Voice Over Packet Solution, Fully Integrated VoP Solution
Duration : August 2000 – Till Date.

Project Description :

The Si was taped out on Oct ‘2001. The Total No. of gates is 1.2 Millions. It operates on 125 MHz. It’s a .18 micron technology. The AD6489 family of packet processors performs voice and data packet processing for the SOHO (Small Office/Home Office). SME (Small & Medium Enterprises and RG (Residential Gateway ) Market. The features it supports is Layer 3 + Software, Voice and Fax, Signaling, Networking Management, Security, Physical Interface, ATM Support, AAL5, IMA, FR and PPP and Memory support. The AD6489 solution helps the system vendor go to market faster by providing a highly -integrated SoC. The SoC comes with a reference board and complete software solution for both VoIP & VoATM based solution. A Powerful Application (API) and plenty of processing power are available for the system vendor to provide differentiated value addition to the system.

Architecture Description :

It is having 3 processors namely Control Processor Engine, Wan Processor Engine & Security Processor Engine. The AHB bus being the major interface between these processor and the Peripherals, which includes like (UTOPIA, HDLC, UART, GPIO, USB, & SPI). There is an intelligent DMA, which does the memory transactions between memory and the processors. Then for the WAN interface we have 10/100 EMAC and also supports external PCI & USB. It has on chip SDRAM controller & flash controller 200KB of on-chip memory for voice and data processing.

Responsibilities :

Developed & Designed in verilog the intelligent DMA block. Which does all the major operation for the above chip AD 6489 the rams.
Created Testbenchs for the blocks like UART, SPI & DMA.
Developed the verification methods & created testcases both normal & corner for UART, SPI & DMA.
Did the RTL & netlist simulation for UART, SPI, DMA.
Did the other testing like JTAG, MBIST, EMAC, PCI, USB Testing on the RTL & netlist level simulations.
Did the random testing for the above blocks at the system levels and also for the other blocks.

Tools Used :

Verilog XL from Cadence 2.37 & Signal Scan/De-bussy for waveforms.

Project : UMAC Design
Duration : Feb’ 00 – July ’00.

Responsibilities :

Designed, developed & verified the UMAC in VERILOG. This s going to be used and cable modem chip. The design was target for APEX FPGA from altera 20K200. The design basically consists of 5 interfaces. Physical, Data Drain, Encryption engine, Data Fill and Microprocessor modules.

The PHY interface can get the data from simultaneously from 8 devices and gives to Data Fill interface via data FIFO. It also stores the relative information in another FIFO called pointer. From these FIFO Data fill interface dumps the data to the memory . The data drain gets from memory and gives to the microprocessor module.

The design operates in 3 different frequencies. The input data is coming at 10Mhz, which is to the phy interface. The microprocessor interface is working on 60 Mhz and the rest of the interface is working on 40Mhz.

Tools Used :

Verilog XL from Cadence 2.37 & Signal Scan/De-bussy for waveforms. Max-Plus II for P & R. Synthesis by Syniplify from synplicity.

Project : SPI Design
Duration : Jan ’00.

Responsibilities :

Implemented the SPI interface in VHDL between SPI and external BUS interface used for IMA.

Tools Used :

Leapfrog Simulation for VHDL

Profile II :

Company : Trenton Chip Devices , Inc.
Location : Sacramento, CA
Designation : VLSI Design Engineer.

Project : Transceiver Subsystem
Duration : Nov’99 – Dec ’99

Responsibilities :

Designed & Developed controller for DPRAM (in verilog) which is used get the Data from ATM fpga and feed to the microprocessor. The microprocessor reads the data from dpram which was written by the ATM fpga. Designed the code in Verilog.

Tool Used :

Compiled and simulated in MTI Verilog simulator (Model Tech). Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics

Project : Internet Data Storage
Duration : Aug’99 – Oct’99

Responsibilities :

To store the Data into the Disk Array through the user in the internet.The block gets the data to be written into the disk module from the memory for which the CPU provides the address. The data with the parity is then stored in the memory. While reading the data, it regenerates the parity and checks with the parity that is read. On error, the date is invalidated.

The parity and data are stored in the memory through the interface. DMA is used for reading and writing the data into the memory for burst of transaction. Developed & Designed the logic in verilog which is specific to Disk Module and it provides the following functions:

Raid Parity generation
Raid Parity verification
Raid Parity reconstruction
Interface to the Main Memory DMA

Tool Used :

Compiled and simulated in MTI Verilog simulator (Model Tech).

Project : OC3_FPGA
Duration : May’99 – July’99

Project Description :

The OC3 FPGA communicates using either ATM Cells or POS. In ATM mode, the data path is between the SAR and the PHY via the UTOPIA slave level 1 to UTOPIA master level 2 interfaces. Utopia1 slave is running on 25 Mhz and data rate is 53 bytes. UTOPIA 2 master is running on 33 Mhz and date rate is 64 bytes. There are two downstream FIFOs and two upstream FIFOs. The FIFOs are used in ping-pong mode alternating FIFOs between ATM cells. No parity or packet error reporting of any kind is supported.

Responsibilities :

Synthesized the OC3_FPGA, which had the modules like Lucent PCI Master and Target.
Module ware Utopia Master and Slave.
Interface Data Path Between Tetra and SAR.
Completed Place and Route of the above project which was mapped with the Orca Foundary Family, of the Architecture 3T800 Series. Totaled to 390 numbers of PFU.

Tool Used :

Synplify Syntheses Tool From Synplicity V 5.1.4.
Lucent Place And Route Tool Version 9.35

Profile III :

Company : Trenton Chip Devices
Location : Chennai, India
Designation : VLSI Design Engineer.

Project : Verification Of USB Open Host Controller
Duration : Jan’ 99 – Apr’99

Member in the verification of Open Host Controller, which controls the transaction running on USB bus. It fetches the Endpoint Descriptor and Transfer Descriptor from memory and performs the appropriate action depends on the information from the Descriptor. These Descriptor includes the information about the device.

Responsibilities :

Developed the PCI Test Bench for OHCI.
Created testcases for the functional verification of OHCI.
Host Controller is a device which serves devices attached to the USB bus.
It is interfaced to the PCI bus for accessing the system memory.
Designed this core using both VHDL and VERILOG.
This design has different types of modules.
1. PCI Master and Target block
2. Open Host Controller block
3. Interface between USB and PCI side
4. Host SIE
5. Root Hub

Project : Design of PCI master/target.
Duration : July’ 98 – Dec’ 98

Designed OHCI compliant PCI master/target function.
Done testing on this module.
Carried out synthesis of all these modules using EXEMPLAR LEONARDO.
Done Place and Route using ALTERA MAX+plusII.

PCI Master initiates transaction on the PCI bus for getting the ED/TD’s or data’s for USB devices from main memory or updating the data from USB devices to main memory.
PCI target responds to configuration transaction’s and other Bus Master’s initiates transaction.

Responsibilities :

Implemented the logic for PCI Target and PCI Master.
Tested the whole project using ModelTech simulator.
Synthesized the logic using Exemplar’s Leonardo tool.
Max+plus II tool is used for Place and Route.
Mapped the PCI core into the Altera Flex10k30 device.
Mapped the USB side core into the Altera Flex10k100A device.
Mapping the whole design into ASIC Library and testing is in progress.
Total gate count for OHCI project is 33,000 gates.

Project : Design and verification of Hearsee-USB Logic
Duration : Jan’98 Jun’98

Project Description :

Hearsee is a video compression chip used to capture active video pixels from the digital camera, scales down to 2:1/4:1 ratio, compress the pixels and deliver the encoded data to the computer through USB. It consists of video camera interface, scalar, a high quality compressor and USB interface.

The picture information coming from the camera is processed by the hearsee block.
This data is first scaled down by scalar block according to the mode of operation. This scaled down data is compressed by the compressor block.
This compressed form of data is sent through the USB cable.

Responsibilities :

Designed the data flow for the still video capture mode of Hearse
Created testcases for the functional verification of Hearsee individually in still, motion capture modes as well as combination of still-live modes
Performed simulation in modeltech VHDL simulator

Project : Verification of USB Device Core
Duration : Nov’ 97 – Dec’ 97

Involved in the verification of a USB Device Core.

Project : Design of FIFO
Duration : Oct’ 97

Designed a 8-bit 256 deep FIFO with revert and latch read pointers. Used Model Tech VHDL/Verilog Simulators and Leonardo Synthesis Tool. Target technology was Altera FLEX10K device.

Project : Design of a bit stuffer
Duration : Sep’97

Designed the bit stuffer in logic works, using VHDL and Verilog.

Project : Design of a Traffic Light Controller and Stepper Motor.
Duration : Aug’ 97

Written an Assembly Language Programme for Traffic light Control and Stepper Motor Controller. Used the add-on card with 8253 Timer and PPI chips along with 8379 for testing of this design.

EDUCATION

Bachelor of Engineering (Electronics and Communication) 1997. Madras University, INDIA. 7.5 GPA.

REFERENCE : Available Upon Request.

Resume 14

Sachin Ravinder

1200 Moonlight Dr.
Santa Clara, CA 95127

VISA Status

Valid H1-B till 2004.

Technical Skills

Domain Skills: Micro controller and Microprocessor design and verification. Understanding of communication Protocols.
Applications: Digital Design Methodology & Network Flow, RTL coding, Synthesis, Simulation of full chip and block level designs. Functional verification of full chip design, Physical design skills at chip level, Physical Verification, Writing Software utilities
Languages: PERL and Shell Script, C, HTML
CAE Tools: Verilog-XL, NCVERILOG, Polaris, Synopsys Synthesis tools, Cadence Composer, Compass tools, DRACULA for physical verification, TransEDA and HDLScore for code coverage, AVANTI tools.
OS: UNIX, SUN-OS, and WINDOWS

Professional Experience

02/01 – present
Network Alliance Corporation
Consultant

Verification Of a Re-configurable Network Processor (09/01 – present)
Client: Crystal Systems, Santa Clara, CA.
Crystal’s CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities require me to write directed tests to verify the tile block and random tests to verify concurrency.

Code Coverage Analysis (07/01 – 08/01)
Client: Vertex Networks, Santa Clara, CA.
My role required me to analyze the test vectors from the viewpoint of code coverage, and furnish suggestions to the verification team as per the findings.

Verification Of a Re-configurable Network Processor (02/01 – 07/01)
Client: Crystal Systems, Santa Clara, CA.
Crystal’s CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities required me to write tests to verify the various modules of the chip, e.g. fabric, road-runner bus, code generator. I also did the code coverage analysis to optimize the test suit for better fault grading.

10/99 – 01/01
Teriola India Ltd., Gurgaon, India
VLSI Design Engineer

Design Of a CAN protocol implementation (11/00 – 01/01)
The Control Area Network (CAN) protocol is used in automobiles for communicating between various controllers inside the vehicle. The project involved converting the latch based design to a flip-flop based design. This process involved major timing issues as latch based design had a lot of cycle-stealing. Responsibilities required me to convert the RTL to flip-flop based design and simulate the design to see there are no issues with the conversion. Finished my part in record time.

Design Of a microcontroller (10/99 – 10/00)
The micro-controller is to be used in automotive Industry for anti-skid braking. It is based on Motorola’s Mcore processors. Responsibilities required me to verify, Synthesize and P&R the Timer block. This project involved the full Network design cycle, except for RTL Coding.

04/98 – 09/99
MARCUS Tech, Bangalore, India
VLSI Design Engineer

Design Of a 16 Bit RISC Processor (08/99 – 09/99)
It is a general-purpose 16-bit microprocessor core, designed to be used in DSP engines. The project involved full chip design using Design Reuse methodology.Responsibilities required me to design, verify and synthesize the Program Counter block.

Functional Verification of a 16 Bit RISC Processor (02/99 – 07/99)
ARC85 is a family of general-purpose 16-bit microprocessor cores, primarily designed for embedded applications. The project involves the Full Chip functional Verification of the microprocessor core. The chip was verified using Compass-generated vectors. I was responsible for writing the test-bench for the full chip simulation. Later, the Compass-generated vectors were used to generate the Verilog format vectors for full chip testing. The work also involved the testing of vectors on the netlist generated by the Synthesis tool. Netlist to RTL conversion was also part of the project.

Redesign of 8-bit Microcontrollers(SPC700 series) for Sony Corp(04/98 – 02/99)
SPC700 series is a general-purpose programmable 8-bit microcontrollers originally designed by SONY. The project involved the redesign of the whole series from 1.4 Micron technology to 0.7 micron tech. It also involved dynamic to static logic conversion. Participated as a member of a 3 member team. Redesigned 2 of a series of 4 microcontrollers. The redesigning involved Logic Conversion, Schematic Entry, PNR and Functional Verification at the block level as well as the full chip level. Played major role in setting up the test environment for the full chip. Executed the project successfully in the first go.

Major Achievements:

Developed a software utility, indigenously, using Perl & Shell scripts to convert the stimulus file from ANDO-DIC 8031/32 format to a Verilog compatible format. This saved a lot of expense to the company.

07/97 – 03/98
Granada Consultancy Services
Assistant System Analyst

American Express Milleniax Conversion (10/97 – 03/98)
The project involved the modification of the existing code for American Express to make it Y2K compliant. The project was divided in various implementation Groups (IG’s). Each IG was responsible for modifying and testing a market. Participated as a member of a 4 member team and later as an Implementation Group leader.

Training in Software Development Process (07/97 – 09/97)
It involved training on different Software Platforms, Programming Languages and Graphical User Interface. It also consisted training on Software Development Methodologies. It also involved a project in C on UNIX to manage an employee database.

Trainings & Workshops

Advanced Chip Synthesis Workshop (2000)
The workshop was conducted by Synopsys Inc. at Teriola, Gurgaon. It focused on advanced chip synthesis methods.

Education

1997 B.Tech. in Electronics & Communication Engg (DGPA 8.28) IT, BHU, Banaras, INDIA

Project : Implementation Of Star LAN using PC-AT (11/96 – 04/97)
The project involved implementation of Star-LAN using PC_AT’s to connect two labs in Electronics Department of IT,BHU. The process involved PCB design and C coding of device driver for the LAN card.

Resume 15

Chen Wong

Toronto, Canada

OBJECTIVE

Sr.chip designer, with MSEE in VLSI, from Nortel Networks, experienced in ASIC, FPGA, HDL, C/C++, ATM, IP 10GE, SONET and RT embedded, applies for ASIC / FPGA design or H/W position.

EDUCATION

MSEE in VLSI Design, ECE of UNB, New Brunswick, Canada.
Ph.D. Candidate in Computer-Aided Design Center, China.
MSCE in Computer Engineering, WU, China.
BSEE in Electrical Engineering, WU, China.

SUMMARY OF QUALIFICATIONS

Skilled in all phases of Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis.
Skilled in Verilog, VHDL and SystemC, Specman, Vera, C/C++ and tools: Synopsys’s DC, Primetime, GNU, VCS, Verilog-XL, NCverilog, Modelsim, SignalScan and Synplify, Xilinx.
Skilled in board level hardware design, Schematic, Simulation, and PCB in OrCAD, Viewlogic.
Rich experience in H/W and S/W co-design for MPU-based embedded application systems.
In-depth working knowledge of ATM, IP, MPLS, GE, SONET and related network protocols, and VLSI devices and theory, ASIC design, CPU architecture, PCI, DSP and firmware development.
Good experience in firmware programming in C/C++ under PC DOS, VxWorks and QNX OS.
Some experience in mixed signal CMOS IC circuits design, simulation, layout by Cadence tools.
Excited by the challenge. A team work player with creative, self-motivated, cooperative spirit.

Work Experience

I have worked in 6 companies and universities in Canada and China in the positions of Senior ASIC Design Engineer, ASIC / FPGA Designer, Lead Hardware Engineer, Hardware Engineer, Firmware Programmer and Research Assistants since I graduated as a MS in Computer Engineering in 1988.

These positions carry over 4-year real experience in ASIC/FPGA/VLSI design, and over 6-year real experience in system and hardware board level development, and 10-year systematic theory studies.

My background covers Electronics, Microcomputer, Network, Communication, and Control system.

Following are my some ASIC/FPGA hardware and system design experience in real world in order:

RELEVANT EXPERIENCE

Vegatron Networks, Toronto, Canada
2001 Oct 1 – present.
Senior ASIC Designer, SoC Architecture Engineer. (Permanent full-time)

Project:

Development of a System-on-Chip ASIC for a new high-performance switching Router.

Skill :

SystemC, C++, GNU/Visual C++ 6.0, Scripts, High Speed I/O, Verilog, DC, PT, VCS, IP protocols.

Responsibility :

Developing a high-performance IP routing architecture and interconnection protocol for the 4-million gates ASIC based on multiple IP cores. Writing a detailed ASIC design specification for RTL design.

Vermax Networks, Ottawa, Canada
May 2001 – Sept 30, 2000
ASIC / FPGA Designer (Permanent full-time)

Project :

10GE Egress Traffic Management ASIC Design.

Skill :

Verilog, Vera, Specman, Tcl, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. RSP2 NP, VSC881 Fabric, MPC 8260, PL4, CSIX, PCI32, 10GE, IP, MPLS, ATM, SONET, POS.

Responsibility :

Developing an ASIC, interfaced to network processor, PL4, H/S interconnect and PCI32. It runs in three clock domains:700MHz, 200MHz, 33MHZ. The main clock is 100MHz. Bandwidth is 10gigabit/s. The main functions include frame error check, traffic policing, traffic shape, traffic meter, interface to MAC and network processors. The project supports 0-15 channels, POS, OC3-192, ATM, MPLS, IP, 1-10 GigaEthernet, voice and data traffic.

Contribution :

Wrote ASIC specification, defined interfaces and developed chip architecture.
Defined and Implemented traffic management algorithms for egress traffic and flow control, Including error check, priority shaping and buffer policing function with optimized structure.
Partitioned core-based design and Coded in Verilog at RTL.
Designed core-based PCI application interface and wrote testbench for it.
Wrote simulation models and performed min. function verification for each block.
Wrote simulation models and performed min. function verification for top level with cores.
Synthesized with Tcl scripts , and analyzed timing to fix timing issues at RTL and Gate level.
Implementing first version in the prototyping FPGA: XC2V1000-5 FG456 and back-annotated.
Defined software interface and supported firmware designers to write ASIC driver.

Vermax Networks, Ottawa, Canada
2000 May – 2001 Sept 30
ASIC / FPGA Designer. (Permanent full-time)

Projects :

OC3 ATM core project: ATM Traffic Executive ASIC Design.
DS3 ATM core project: ATM Traffic Executive FPGA Design.

Skill :

Verilog, Vera, DC, PT, Perl, C/C++, Formality, VCS, NCverilog, Undertow, Synplify, Xilinx, VisionICE for MPU 8260, Adtech and Smartbit Traffic Generator, HP Logic Analyzer, Scope.

Responsibility :

Deveopled a chip as an ATM traffic scheduler. It works as part of MMC fabric chipset. It runs in two clock domains: 50MHz and 20MHz. Total 512 traffic schedulers are required.

Contribution :

Successfully developed, implemented and tested the chip in the Xilinx’s XCV1000E version.
Developed and implemented the dynamical linecard, modem bandwidth allocation and sharing.
Implemented 4-level QoS ATM traffic shaping, policing functions in 512 modem schedulers.
Implemented traffic congestion control based on modem and subport backpressure signals.
Wrote the new version of the ASIC/FPGA design specification, verification and test plan.
Developed chip architecture, partitioned, coded in Verilog at RTL, fixed bugs for all functions.
Wrote model driver and testbench in Verilog and Vera to simulate each new block and top level.
Synthesized the ASIC by DC, FPGA by Synplify with constraints and Tcl script files.
Used Synopsys ‘s DC and PT timing analysis for timing debug and timing closure.
Wrote test script for VxWorks dshell and VisionICE to test traffic in lab by Adtech, Smartbit.

Note: I was awarded Vermax’s Gold Pride Award due to dedication to the scheduler chip in 2000.

VLSI Lab of ABC, New Brunswick, Canada
1997 Sept – 2000 April

Project:

ATM Simulator FPGA Design Utilizing PCI Bus

Skill :

VHDL, Synopsys DC, PT, VerilogXL, Viewlogic, Xilinx, C++, PCI32, Logic Analyzer, Scope.

Responsibility :

Developed an ASIC/FPGA chip for a low cost, high performance ATM simulator to help in the research and teaching of ATM networks in real world in cooperation of EE and CS departments.

Contribution :

Successfully developed, implemented and tested the ATM chip in the XC4062XLA-09.
Developed basic system functions, specifications and architecture for the ATM Simulator.
Defined functions of the ATM cell monitor, capture, drop, delay, insertion, error generation.
Created a VHDL design flow, partitioned the chip, and coded in VHDL at RTL.
Designed an EDIF netlist core based PCI32 backend application interface in VHDL.
Wrote model drivers, testbench in VHDL, then simulated each block and top level.
Synthesized by Synopsys’s Design Compiler. Timing debug and closure by Primetime.
Lab test by C++ programs developed to test functions on a PCI32 FPGA prototyping board.

VLSI Lab of ABC, New Brunswick, Canada
1997 Sept – 2000 April

Project :

Some Course Projects in VLSI and Real-time OS.

Skill :

Verilog, Vera, Specman, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx.

Responsibility :

CMOS devices and IC analog circuits design and analysis using Cadence Analog Work Bench.
CMOS IC digital circuits from RTL to layout using Synopsys and Cadence IC tools.
Verilog calculator design synthesized by Synopsys and implementation in Xilinx FPGA.
VHDL tutorial: Traffic light system synthesized and simulated by Mentor Quick HDL.
Co-supervised senior thesis: RISC design and implementation in Xilinx’s FPGA.
Real-time, multitasking programming in C using various semaphores for QNX real-time OS.

Diamond Graphics Inc, Ontario, Canada
1996 Sept – 1997 Aug
Hardware Engineer, FPGA Designer. (Permanent full-time)

Project :

Development of MCU-based Controller for a graphic scanner.

Skill :

Synplify, Xilinx FPGA, OrCAD Schematic and PCB, PC DOS and MCU programming in C.

Responsibility :

Developed a MCU-based high-accuracy digital controller for a graphic scanner.

Contribution :

Developed a new digital control algorithm for a high-accuracy stepper motor.
Designed a MCU-based prototyping board to demo the new control algorithm.
FPGA design in Xilinx F1.5, and board schematic and PCB design in OrCAD.
PC DOS programming and MCU 8051 firmware programming in C.

Digital Design Center, Wuhan, China
1994 Sept – 1996 June

Project :

Ph.D. Project. Computer-based Non-contact Microsurface Online Measurement.

Skill :

Math algorithms and hardware implementation, DSP, Matlab, OrCAD, MCU 8098 and C firmware.

Responsibility :

Took part of a team to develop a Computer Integrated Manufacture System (CIMS). Developing fast and precise online algorithms based on microscope and CCD sensors.

Contribution :

Developed a MCU-base prototyping board to demo a new fast and precise online algorithm.

Teinan Tiger Computer Inc, China
1988 June – 1994 Aug.
Lead Hardware Engineer, System Engineer. (Permanent full-time)

Project :

Computer-based Data Acquisition Network System Development.

Skill :

PC-based Application System design, Digital and Analog Board design, MCU Firmware in C.

Responsibility :

Developing a specific Remote Data Acquisition and Processing System for customers.

Contribution :

Leaded a team to successfully develop some computer-based data acquisition network systems, typically which have over 1000 points and are over 100Km away from host control room.
Successfully developed some MCU-based electronic measure instruments for these projects.
Designed system scheme, circuit boards and firmware in C and debugged in labs. Supports.

Teinan Tiger Computer Inc, China
1988 June – 1994 Aug
Hardware Engineer, Firmware Programmer. (Permanent full-time)

Project :

An electronic teaching laboratory Development.

Skill :

Schematic and PCB design in Protel, GAL, PAL, 8051 and firmware in C, DOS programming in C.

Responsibility :

Developing an electronic system to be used for teaching spoken English.

Contribution :

Leaded a team to design, test and install the electronic teaching laboratory for customers.
Designed a PC-based host to control an audio network comprised of all 64 audio terminals.
Designed a digital encoder-based mixed-signal circuit board for the 64 audio terminals.

Department of Computer Engineering, Wuhan University, China
1985 Sep -1988 May

Project :

Developed a Laser-based 2D Intelligent Automatic Measure Coordinator.

Skill :

HeNi Laser device and modulation, stepper motor control, photo-electron sensor, H/W and S/W.

Responsibility :

Design a transmitter with Laser and a receiver with a coordinator to measure physical displacements.

Contribution :

Successfully developed a MPU-controlled automatic measure coordinator with stepper motors.
Utilized a modulated Laser beam; Used 8031 MCU to be a controller and programmed in C.

Skills Training:

Training Courses at Nortel Networks from 2000 to 2001.

Advanced DC Synthesis Workshop.
Synopsys’s VERA HVL Workshop
High-level Chip Design in Verilog.
Verification Strategies in Verilog
High-Speed Circuit Design.
Primetime Training Workshop
PowerPC 8260 Workshop.
Tornado Training Workshop

Master Degree Courses (1997-1999 in EE and CS ) GPA = 87% ( 4.0 / 4.3 )

EE6123 Semiconductor Devices ( CMOS Modeling )
EE4173 Devices and circuits for VLSI ( CMOS IC processing )
EE6133 VLSI Circuits Design ( analog VLSI circuits )
EE6213 ASIC Design ( digital ASIC design )
CS6812 Computer Aided Logic Design ( logic methodology )
CS6845 Computer Networks and Open Systems ( IP Networks )
EE4243 Data Communications ( Modem, Ethernet )
EE4273 Real Time Operation of Microcomputers (RT Programming )
EE6373 Signal Processor Architecture EE4543 DSP II ( digital filter design )
CS4815 Advanced Computer Architecture CS5865 Data Networks II